MLCAD: A survey of research in machine learning for CAD keynote paper

M Rapp, H Amrouch, Y Lin, B Yu… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

Progress and challenges in VLSI placement research

IL Markov, J Hu, MC Kim - … of the International Conference on Computer …, 2012 - dl.acm.org
Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

Maskplace: Fast chip placement via reinforced visual representation learning

Y Lai, Y Mu, P Luo - Advances in Neural Information …, 2022 - proceedings.neurips.cc
Placement is an essential task in modern chip design, aiming at placing millions of circuit
modules on a 2D chip canvas. Unlike the human-centric solution, which requires months of …

Replace: Advancing solution quality and routability validation in global placement

CK Cheng, AB Kahng, I Kang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
The Nesterov's method approach to analytic placement has recently demonstrated strong
solution quality and scalability. We dissect the previous implementation strategy and show …

ePlace: Electrostatics-based placement using fast fourier transform and Nesterov's method

J Lu, P Chen, CC Chang, L Sha, DJH Huang… - ACM Transactions on …, 2015 - dl.acm.org
We develop a flat, analytic, and nonlinear placement algorithm, ePlace, which is more
effective, generalized, simpler, and faster than previous works. Based on the analogy …

ePlace-MS: Electrostatics-based placement for mixed-size circuits

J Lu, H Zhuang, P Chen, H Chang… - … on Computer-Aided …, 2015 - ieeexplore.ieee.org
We propose an electrostatics-based placement algorithm for large-scale mixed-size circuits
(ePlace-MS). ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling …

Benchmarking end-to-end performance of ai-based chip placement algorithms

Z Wang, Z Geng, Z Tu, J Wang, Y Qian, Z Xu… - arXiv preprint arXiv …, 2024 - arxiv.org
The increasing complexity of modern very-large-scale integration (VLSI) design highlights
the significance of Electronic Design Automation (EDA) technologies. Chip placement is a …

ePlace-3D: Electrostatics based placement for 3D-ICs

J Lu, H Zhuang, I Kang, P Chen… - Proceedings of the 2016 on …, 2016 - dl.acm.org
We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension
integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) …

Hierarchical reinforcement learning for chip-macro placement in integrated circuit

Z Tan, Y Mu - Pattern Recognition Letters, 2024 - Elsevier
The complexity of chip design has consistently grown, adhering to Moore's law. In this paper,
we examine a crucial step in integrated circuit design called chip macro placement …

POLAR 3.0: An ultrafast global placement engine

T Lin, C Chu, G Wu - 2015 IEEE/ACM International Conference …, 2015 - ieeexplore.ieee.org
Placement is one of the most important problems in electronic design automation. Although
it has been investigated for several decades, a more efficient core engine is critically needed …