mmWave communications for 5G: implementation challenges and advances

L Li, D Wang, X Niu, Y Chai, L Chen, L He… - Science China …, 2018 - Springer
The requirement of the fifth generation (5G) wireless communication for high throughput
motivates the wireless industry to use the mmWave (millimeter wave) communications for its …

A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS

W Wu, RB Staszewski, JR Long - IEEE Journal of solid-state …, 2014 - ieeexplore.ieee.org
A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with
wideband frequency modulation (FM) for FMCW radar applications is proposed. The …

Design of low-voltage power efficient frequency dividers in folded MOS current mode logic

F Centurelli, G Scotti, A Trifiletti… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
In this paper we propose a methodology to design high-speed, power-efficient static
frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) …

A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment

Z Tibenszky, M Kreißig, C Carta… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This research work presents the analysis, design, and characterization of a concept for an
mm-wave divide-by-4 frequency divider utilizing an extended true single-phase clock (E …

A 60-GHz CMOS broadband receiver with digital calibration, 20-to-75-dB gain, and 5-dB noise figure

Y Chai, X Niu, L He, L Li, TJ Cui - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
We present a 60-GHz broadband heterodyne receiver with digital calibration. In the LNA, the
low-coupling coefficient transformer-based matching network and the tail switch technique …

A 25–102GHz 2.81–5.64 mW tunable divide-by-4 in 28nm CMOS

M Vigilante, P Reynaert - 2015 IEEE Asian Solid-State Circuits …, 2015 - ieeexplore.ieee.org
A wideband tunable divide-by-4 is designed and realized in 28nm bulk CMOS. A systematic
design methodology to maximize the locking range over power consumption ratio is …

Design of an inductor-less 72-GHz 2: 1 CMOS CML frequency divider with dual-core VCO

E Chou, L Iotti, A Niknejad - … on Circuits and Systems II: Express …, 2022 - ieeexplore.ieee.org
This brief presents the modeling and design of a static current-mode logic, divide-by-2
frequency divider for mm-wave frequency synthesis. An optimized design procedure based …

A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes

E Abiri, A Darabi - Microprocessors and Microsystems, 2018 - Elsevier
In this work, a novel architecture is proposed for designing the clocked master-slave TFF
(M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used …

A 3.9 mw 1–39 GHz static frequency divider employing series inductive peaking technique

B Jiang, J Feng, W Li - 2014 IEEE International Symposium on …, 2014 - ieeexplore.ieee.org
This paper presents a power efficient static frequency divider (SFD) for wideband operation.
Series inductive peaking technique is utilized to construct broadband input network of the …

Design and measurement techniques for an 80 Gb/s 1-tap decision feedback equalizer

A Awny, L Moeller, J Junio, JC Scheytt… - IEEE Journal of Solid …, 2013 - ieeexplore.ieee.org
A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision
feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On …