[PDF][PDF] Structural stationarity in the π-calculus.
R Meyer - 2009 - researchgate.net
Structural Stationarity in the -Calculus Page 1 Introduction to π-Calculus Structural Semantics
Structural Stationarity Decidability in Bounded Depth Structural Stationarity in the π-Calculus …
Structural Stationarity Decidability in Bounded Depth Structural Stationarity in the π-Calculus …
A practical approach to verification of mobile systems using net unfoldings
We propose a technique for verification of mobile systems. We translate finite control
processes, a well-known subset of π-Calculus, into Petri nets, which are subsequently used …
processes, a well-known subset of π-Calculus, into Petri nets, which are subsequently used …
Specification and formal verification of temporal properties of production automation systems
This article describes our approach for the specification and verification of production
automation systems with real-time properties. We focus on the graphical MFERT notation …
automation systems with real-time properties. We focus on the graphical MFERT notation …
[图书][B] Entwicklung von Methoden zur abstrakten Modellierung von Automotive Systems-on-Chips
A Kirchner - 2022 - library.oapen.org
Abstract Diese Open-Access-Publikation bietet zu Beginn einen Einblick in die Grundlagen
der modellbasierten Systementwicklung. Dabei analysiert die Publikation aktuell …
der modellbasierten Systementwicklung. Dabei analysiert die Publikation aktuell …
[PDF][PDF] Parallel bounded property checking with SymC
Today, verification of industrial size designs like multi-million gate ASICs (Application
Specific Integrated Circuit) and SoC (System-on-a-Chip) processors consumes up to 75% of …
Specific Integrated Circuit) and SoC (System-on-a-Chip) processors consumes up to 75% of …
Overlap reduction in symbolic system traversal
PM Peranandam, PK Nalla, RJ Weiss… - … High-Level Design …, 2005 - ieeexplore.ieee.org
A divide-and-conquer approach in BDD-based verification to handle larger designs is to
partition BDDs exceeding a threshold size and to deal with the partitions separately …
partition BDDs exceeding a threshold size and to deal with the partitions separately …
Distributed symbolic bounded property checking
PK Nalla, RJ Weiss, P Peranandam, J Ruf… - Electronic Notes in …, 2006 - Elsevier
In this paper we describe an algorithm for distributed, BDD-based bounded property
checking and its implementation in the verification tool SymC. The distributed algorithm …
checking and its implementation in the verification tool SymC. The distributed algorithm …
Efficient Distributed Bounded Property Checking
PK Nalla - 2008 - ub01.uni-tuebingen.de
Today, verification of industrial size designs like multi-million gate ASICs (Application
Specific Integrated Circuit) and SoC (System-on-a-Chip) processors consumes up to 75% of …
Specific Integrated Circuit) and SoC (System-on-a-Chip) processors consumes up to 75% of …
Specification and verification of SOC using PTL
P Zhang - 2009 Asia-Pacific Conference on Computational …, 2009 - ieeexplore.ieee.org
PTL (projection temporal logic) is a kind of temporal logic which can handle both sequential
and parallel computation. In this paper, we proposed a formal approach of specification and …
and parallel computation. In this paper, we proposed a formal approach of specification and …
Formal Specification of RTL-Level Digital System Using Projection Temporal Logic
PF Zhang - Applied Mechanics and Materials, 2015 - Trans Tech Publ
An approach to specify a RTL-level system using Projection Temporal Logic (PTL) is
proposed in this paper. With this approach, a digital system described with Register Transfer …
proposed in this paper. With this approach, a digital system described with Register Transfer …