Energy efficient counter design using voltage scaling on FPGA
In this work, we are using voltage scaling to make the counter design as an energy efficient
design. The 74163 counter is a 4-bit fully synchronous counter that is available in both TTL …
design. The 74163 counter is a 4-bit fully synchronous counter that is available in both TTL …
HSTL IO standard based energy efficient multiplier design using Nikhilam navatashcaramam dashatah on 28nm FPGA
In this paper we have designed an energy efficient multiplier using Nikhilam
Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and …
Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and …
SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA
M Bansal, N Bansal, R Saini, B Pandey… - 3rd International …, 2014 - ieeexplore.ieee.org
Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the
impedance of line, port and device of our design under consideration. Therefore, selection of …
impedance of line, port and device of our design under consideration. Therefore, selection of …
[PDF][PDF] SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices
Now days green computing is major research area in the computer science field, where we
want to reduce the total power consumption of our device by applying different techniques …
want to reduce the total power consumption of our device by applying different techniques …
Lvttl and sstl io standards based energy efficient fsm design on 16nm ultrascale plus fpga
Reducing power dissipation of any device at design stage leads to saving of power
consumption in the lifetime of the device that eventually results in saving of energy and …
consumption in the lifetime of the device that eventually results in saving of energy and …
Energy efficient flip flop design using voltage scaling on FPGA
In this work, we are using voltage scaling and frequency scaling. In voltage scaling, voltage
is scaled from 3V to 1V, where intermediate values are 2.5 V, 2V, 1.8 V and 1.5 V. In …
is scaled from 3V to 1V, where intermediate values are 2.5 V, 2V, 1.8 V and 1.5 V. In …
Capacitance scaling with different IO standard based energy efficient bio-medical wrist watch design on 28nm FGPA
In this paper, we have designed an energy efficient wrist watch on 28nm FPGA. The code
has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T …
has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T …
[DOC][DOC] Frequency Scaling Based Power Efficient Kannada Unicode Reader Design on 40nm and 28nm FPGA
In the following paper Kannada Unicode Reader has been designed which is then made
energy and power efficient by employing Energy Efficient Technique at 2 different FPGA …
energy and power efficient by employing Energy Efficient Technique at 2 different FPGA …
Input–Output Standard-Based Energy Efficient UART Design on 90ánm FPGA
R Sharma, B Pandey, V Jha, S Saurabh… - System and Architecture …, 2018 - Springer
This paper illustrates the behavior of the UART in response to the various I/O standards.
Research has been carried out to find out the most ideal standard for UART design which …
Research has been carried out to find out the most ideal standard for UART design which …
I/O StandardsBased on Green Communication UsingFibonacci GeneratorDesign on FPGA
S Nagah, B Pandey, K Kalia, R Kaur… - International Journal of …, 2015 - earticle.net
In this paper LVCMOS, HSLVDCI, HSTL, LVDCI_DV2 and SSTL Input/output standard is
used for the design of Green Fibonacci generator on 40nm FGPA to generate key for Wi-Fi …
used for the design of Green Fibonacci generator on 40nm FGPA to generate key for Wi-Fi …