One of the most important industrial applications of SAT is currently Bounded Model
Checking (BMC). This technique is typically used for formal hardware verification in the …

Reinforcement learning (RL) depends critically on the choice of reward functions used to
capture the desired behavior and constraints of a robot. Usually, these are handcrafted by a …

Abstract Model checking is an automatic verification technique for hardware and software
systems that are finite state or have finite state abstractions. It has been used successfully to …

We consider the problem of bounded model checking (BMC) for linear temporal logic (LTL).
We present several efficient encodings that have size linear in the bound. Furthermore, we …

Bounded model checking is an efficient method for finding bugs in system designs. The
major drawback of the basic method is that it cannot prove properties, only disprove them …

Modern satisfiability (SAT) solvers have become the enabling technology of many model
checkers. In this chapter, we will focus on those techniques most relevant to industrial …

Abstract Model checkers and sequential equivalence checkers have become essential tools
for the semiconductor industry in recent years. The Hardware Model Checking Competition …

The reactive synthesis problem consists of automatically producing correct-by-construction
operational models of systems from high-level formal specifications of their behaviours …

We consider the problem of bounded model checking for linear temporal logic with past
operators (PLTL). PLTL is more attractive as a specification language than linear temporal …

The recent extensive availability of 'cloud'computing platforms is very appealing for the
formal verification community. In fact, these platforms represent a great opportunity to run …