Fully digital feedforward background calibration of clock skews for sub-sampling TIADCs using the polyphase decomposition

H Le Duc, DM Nguyen, C Jabbour… - … on Circuits and …, 2017 - ieeexplore.ieee.org
This paper presents a low-power fully digital clock skew feedforward background calibration
technique in sub-sampling Time-Interleaved Analog-to-Digital Converters (TIADCs). Both …

Analog to digital converter device and method of calibrating clock skew

WJ Kang, YC Chen, LAM Man-Pio - US Patent 10,784,882, 2020 - Google Patents
An analog to digital converter (ADC) device includes ADC circuitries, a calibration circuitry,
and a skew adjustment circuitry. The ADC circuitries are configured to convert an input …

Method and apparatus to reduce effect of dielectric absorption in SAR ADC

S Monangi, M Madhavan - US Patent 10,256,831, 2019 - Google Patents
(57) ABSTRACT A successive approximation register analog to digital con verter (SAR ADC)
is provided in which impact of dielectric absorption is reduced with a correction circuit …

Multi-channel interleaved analog-to-digital converter (ADC) using overlapping multi-phase clocks with SAR-searched input-clock delay adjustments and background …

CF Lok - US Patent 11,646,747, 2023 - Google Patents
US11646747B1 - Multi-channel interleaved analog-to-digital converter (ADC) using
overlapping multi-phase clocks with SAR-searched input-clock delay adjustments and …

Close-in tones

S Ramakrishnan, J Tangudu, S Venkatraman… - US Patent …, 2015 - Google Patents
A system can include a close-in tone control configured to detect a set of close-in tones of an
interleaved analog to digital converter (IADC) signal and output a trigger signal in response …

Apparatus for calibrating a time-interleaved analog-to-digital converter

M Camponeschi, A Molina - US Patent 10,868,556, 2020 - Google Patents
An apparatus for calibrating a time-interleaved analog-to digital converter including a
plurality of time-interleaved analog-to-digital converter circuits is provided. The appa ratus …

Method and apparatus to reduce effect of dielectric absorption in SAR ADC

S Monangi, M Madhavan - US Patent 10,615,812, 2020 - Google Patents
(57) ABSTRACT A successive approximation register analog to digital con verter (SAR ADC)
is provided in which impact of dielectric absorption is reduced with a correction circuit …

Pattern based estimation of errors in ADC

SKR Naru, VP Appala, S Dusad, N Shrivastava… - US Patent …, 2018 - Google Patents
An ADC includes a flash ADC. The flash ADC generates a flash output in response to an
input signal, and an error correction block generates a known pattern. A selector block is …

Timing skew mismatch calibration for time interleaved analog to digital converters

A Bal, V Singh - US Patent 12,009,830, 2024 - Google Patents
A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured
to sample and convert an input analog signal to generate a first digital signal and a second …

Matrix processor generating SAR-searched input delay adjustments to calibrate timing skews in a multi-channel interleaved analog-to-digital converter (ADC)

CF Lok, ZJ Li - US Patent 11,641,210, 2023 - Google Patents
US11641210B1 - Matrix processor generating SAR-searched input delay adjustments to
calibrate timing skews in a multi-channel interleaved analog-to-digital converter (ADC) - Google …