Area-selective deposition: fundamentals, applications, and future outlook
GN Parsons, RD Clark - Chemistry of Materials, 2020 - ACS Publications
This review provides an overview of area-selective thin film deposition (ASD) with a primary
focus on vapor-phase thin film formation via chemical vapor deposition (CVD) and atomic …
focus on vapor-phase thin film formation via chemical vapor deposition (CVD) and atomic …
Materials to systems co-optimization platform for rapid technology development targeting future generation CMOS nodes
Design technology co-optimization (DTCO) has been a workhorse in optimizing logic
technology innovations for a few generations now. With increased complexity associated …
technology innovations for a few generations now. With increased complexity associated …
Electrical coupling effect of forksheet FET for power, performance, and area analysis
We analyze the electrical coupling effect of a fork-shaped field-effect transistor (FSFET) and
compare FSFET and the nanosheet FET (NSFET) in terms of logic cell power, performance …
compare FSFET and the nanosheet FET (NSFET) in terms of logic cell power, performance …
Semi-damascene integration of a 2-layer MOL VHV scaling booster to enable 4-track standard cells
V Vega-Gonzalez, D Radisic… - 2022 International …, 2022 - ieeexplore.ieee.org
A new cell routing architecture called vertical-horizontal-vertical (VHV) which requires a two-
level (2L) middle-of-line (MOL) scheme has been proposed as a scaling booster to enable 4 …
level (2L) middle-of-line (MOL) scheme has been proposed as a scaling booster to enable 4 …
Standard cell architectures for N2 node: transition from FinFET to nanosheet and to forksheet device
B Chehab, P Weckx Sr, J Ryckaert Sr… - … Co-optimization for …, 2020 - spiedigitallibrary.org
N2 node is introduced at 42nm poly pitch (CPP), 16 metal pitch (MP) by using 5 tracks (5T)
cell height, single fin, and buried power rail (BPR). Due to the extreme cell height reduction …
cell height, single fin, and buried power rail (BPR). Due to the extreme cell height reduction …
Improving performance and power by co-optimizing middle-of-line routing, pin pattern generation, and contact over active gates in standard cell layout synthesis
S Chung, J Jeong, T Kim - Proceedings of the ACM/IEEE International …, 2022 - dl.acm.org
This paper addresses the combined problem of the three core tasks, namely routing on the
middle-of-line (MOL) layer, generating I/O pin patterns (PP), and allocating contacts over …
middle-of-line (MOL) layer, generating I/O pin patterns (PP), and allocating contacts over …
Characterization of Silicon FinFETs under Nanoscale Dimensions
Silicon fin-shaped field-effect transistors (FinFETs) have been first introduced in 22 nm node
by enhancing gate-to-channel controllability over planar MOSFETs. As the self-aligned …
by enhancing gate-to-channel controllability over planar MOSFETs. As the self-aligned …
Sequential 3D standard cell 4T architecture using design crenellation and self-aligned MOL for N2 technology and beyond
As traditional pitch scaling is losing steam, 3D logic is being explored to further extend
density scaling as an alternative to continued standard cell scaling. This paper will discuss …
density scaling as an alternative to continued standard cell scaling. This paper will discuss …