A survey of timing verification techniques for multi-core real-time systems
This survey provides an overview of the scientific literature on timing verification techniques
for multi-core real-time systems. It reviews the key results in the field from its origins around …
for multi-core real-time systems. It reviews the key results in the field from its origins around …
A survey on cache management mechanisms for real-time embedded systems
Multicore processors are being extensively used by real-time systems, mainly because of
their demand for increased computing power. However, multicore processors have shared …
their demand for increased computing power. However, multicore processors have shared …
Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
Deeppicar: A low-cost deep neural network-based autonomous car
MG Bechtel, E McEllhiney, M Kim… - 2018 IEEE 24th …, 2018 - ieeexplore.ieee.org
We present DeepPicar, a low-cost deep neural network based autonomous car platform.
DeepPicar is a small scale replication of a real self-driving car called DAVE-2 by NVIDIA …
DeepPicar is a small scale replication of a real self-driving car called DAVE-2 by NVIDIA …
Making huge pages actually useful
The virtual-to-physical address translation overhead, a major performance bottleneck for
modern workloads, can be effectively alleviated with huge pages. However, since huge …
modern workloads, can be effectively alleviated with huge pages. However, since huge …
Taming non-blocking caches to improve isolation in multicore real-time systems
In this paper, we show that cache partitioning does not necessarily ensure predictable cache
performance in modern COTS multicore platforms that use non-blocking caches to exploit …
performance in modern COTS multicore platforms that use non-blocking caches to exploit …
Deterministic memory hierarchy and virtualization for modern multi-core embedded systems
One of the main predictability bottlenecks of modern multi-core embedded systems is
contention for access to shared memory resources. Partitioning and software-driven …
contention for access to shared memory resources. Partitioning and software-driven …
Denial-of-service attacks on shared cache in multicore: Analysis and prevention
In this paper we investigate the feasibility of denial-of-service (DoS) attacks on shared
caches in multicore platforms. With carefully engineered attacker tasks, we are able to cause …
caches in multicore platforms. With carefully engineered attacker tasks, we are able to cause …
A first look at RISC-V virtualization from an embedded systems perspective
This article describes the first public implementation and evaluation of the latest version of
the RISC-V hypervisor extension (H-extension v0. 6.1) specification in a Rocket chip core …
the RISC-V hypervisor extension (H-extension v0. 6.1) specification in a Rocket chip core …
A survey of techniques for reducing interference in real-time applications on multicore platforms
T Lugo, S Lozano, J Fernández, J Carretero - IEEE Access, 2022 - ieeexplore.ieee.org
This survey reviews the scientific literature on techniques for reducing interference in real-
time multicore systems, focusing on the approaches proposed between 2015 and 2020. It …
time multicore systems, focusing on the approaches proposed between 2015 and 2020. It …