Low-power and variation-aware approximate arithmetic units for image processing applications
M Mirzaei, S Mohammadi - AEU-International Journal of Electronics and …, 2021 - Elsevier
In applications such as image processing and machine learning, imprecision can be
tolerated because of the nature of the application itself or the limitation of human senses. By …
tolerated because of the nature of the application itself or the limitation of human senses. By …
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework
The complexity of manycore System-on-chips (SoCs) is growing faster than our ability to
manage them to reduce the overall energy consumption. Further, as SoC design moves …
manage them to reduce the overall energy consumption. Further, as SoC design moves …
Aggressive GPU cache bypassing with monolithic 3D-based NoC
CT Do, CH Kim, SW Chung - The Journal of Supercomputing, 2023 - Springer
Cache bypassing is widely employed to alleviate cache contention and pollution in GPUs.
However, cache bypassing often puts more pressure on the network-on-chip (NoC) since …
However, cache bypassing often puts more pressure on the network-on-chip (NoC) since …
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple
memory and logic layers in a single chip with fine-grained connections. M3D technology …
memory and logic layers in a single chip with fine-grained connections. M3D technology …
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple
memory and logic layers in a single chip with fine-grained connections. M3D technology …
memory and logic layers in a single chip with fine-grained connections. M3D technology …