Memory device to train neural networks
VS Ramesh - US Patent App. 15/931,664, 2021 - Google Patents
Methods, systems, and apparatuses related to training neural networks are described. For
example, data management and training of one or more neural networks may be …
example, data management and training of one or more neural networks may be …
Method, unit and circuit for implementing boolean logic based on computing-in-memory transistor
GU Jiani, B Chen, X Yu, JIN Chengji… - US Patent App. 18 …, 2023 - Google Patents
US20230223939A1 - Method, unit and circuit for implementing boolean logic based on
computing-in-memory transistor - Google Patents US20230223939A1 - Method, unit and …
computing-in-memory transistor - Google Patents US20230223939A1 - Method, unit and …
Processing-in-memory (PIM) devices
CK Song - US Patent 11,474,787, 2022 - Google Patents
A processing-in-memory (PIM) device includes a plurality of storage regions, a global buffer,
and a plurality of multiplication/accumulation (MAC) circuits. The plurality of MAC circuits are …
and a plurality of multiplication/accumulation (MAC) circuits. The plurality of MAC circuits are …
Methods and systems for processing read-modify-write requests
GS Goldman, A Radhakrishnan - US Patent 11,630,605, 2023 - Google Patents
US11630605B1 - Methods and systems for processing read-modify-write requests - Google
Patents US11630605B1 - Methods and systems for processing read-modify-write requests …
Patents US11630605B1 - Methods and systems for processing read-modify-write requests …
Adaptive scheduling of memory and processing-in-memory requests
Adaptive scheduling of memory requests and processing-in-memory requests is described.
In accordance with the described techniques, a memory controller receives a plurality of …
In accordance with the described techniques, a memory controller receives a plurality of …
Memory device performing in-memory operation and method thereof
SW Kim, P Yoonah, KIM Changhyun… - US Patent 12,032,829, 2024 - Google Patents
Disclosed is a memory device including a plurality of memory banks, each of which performs
an operation based on first operand data including pieces of first unit data and second …
an operation based on first operand data including pieces of first unit data and second …
Banked memory architecture for multiple parallel datapath channels in an accelerator
SS Youn, SK Reinhardt, H Geng - US Patent 11,704,251, 2023 - Google Patents
The present disclosure relates to devices and methods for using a banked memory structure
with accelerators. The devices and methods may segment and isolate dataflows in datapath …
with accelerators. The devices and methods may segment and isolate dataflows in datapath …
Command throughput in PIM-enabled memory using available data bus bandwidth
J Alsop, AGA Shaizeen, N Jayasena - US Patent 11,262,949, 2022 - Google Patents
US11262949B2 - Command throughput in PIM-enabled memory using available data bus
bandwidth - Google Patents US11262949B2 - Command throughput in PIM-enabled memory …
bandwidth - Google Patents US11262949B2 - Command throughput in PIM-enabled memory …