A comparison of synchronous and cycle-static dataflow

TM Parks, JL Pino, EA Lee - Conference Record of The Twenty …, 1995 - ieeexplore.ieee.org
We compare synchronous dataflow (SDF) and cyclo-static dataflow (CSDF), which are each
special cases of a model of computation we call dataflow process networks. In SDF actors …

Frequency and power correlation between at-speed scan and functional tests

S Sde-Paz, E Salomon - 2008 IEEE International Test …, 2008 - ieeexplore.ieee.org
At-speed scan is a key technique in modern IC testing. One of its drawbacks, with respect to
functional tests, is its excessive power consumption leading to voltage drop and frequency …

A novel approach for implementing conventional LBIST by high execution microprocessors

C Shravani, GR Krishna, HL Bollam… - … on Smart Systems …, 2022 - ieeexplore.ieee.org
The major VLSI circuits like sequential circuits, linear chips and op amps are very important
elements to provide many logic functions. Today's competitive devices like cell phone, tabs …

Using dependence analysis to support the software maintenance process

JP Loyall, SA Mathisen - 1993 Conference on Software …, 1993 - ieeexplore.ieee.org
Dependence analysis is useful for software maintenance because it indicates the possible
effects of a software modification on the rest of a program. This helps the software maintainer …

Understanding power supply droop during at-speed scan testing

P Pant, J Zelman - 2009 27th IEEE VLSI Test Symposium, 2009 - ieeexplore.ieee.org
The paper explores the effects of power-supply droop during scan based at-speed test
application. The unnatural supply voltage profile that results when the capture clocks are …

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects

S Hellebrand, T Indlekofer… - 2014 International …, 2014 - ieeexplore.ieee.org
Small delay faults may be an indicator of a reliability threat, even if they do not affect the
system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a …

Deep learning strategies for labeling and accuracy optimization in microcontroller performance screening

N Bellarmino, R Cantoro, M Huch… - … on Computer-Aided …, 2024 - ieeexplore.ieee.org
In safety-critical applications, microcontrollers must be compliant with the required quality
constraints and performance standards, particularly in terms of the maximum operating …

Performance screening using functional path ring oscillators

T Kilian, D Tille, M Huch, M Hanel… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The testing of integrated circuits is an important topic, particularly in safety-critical
applications. This is especially true for microcontrollers (MCUs) used in the automotive …

Voltage transient detection and induction for debug and test

R Petersen, P Pant, P Lopez, A Barton… - 2009 International …, 2009 - ieeexplore.ieee.org
Voltage transients from circuit activity impact operation, testing and debug of complex
designs. This paper describes a system which enables voltage transient detection and a …

Automatic BRAM testing for robust dynamic voltage scaling for FPGAs

I Ahmed, S Zhao, J Meijers… - … Conference on Field …, 2018 - ieeexplore.ieee.org
Recently FPGA researchers have proposed different approaches to enable dynamic voltage
scaling (DVS) for FPGAs. While the proposed approaches have shown that DVS is able to …