Apparatus, systems and methods are described including dividing cache lines into at least
most significant portions and next most significant portions, storing cache line contents in a …

Instructions and logic provide SIMD vector population count functionality. Some
embodiments store in each data field of a portion of n data fields of a vector register or …

Instructions and logic provide vector compress and rotate functionality. Some embodiments,
responsive to an instruction specifying: a vector source, a mask, a vector destination and …

According to one technique, a virtual machine identifies a first instruction to create a variable
handle instance, the first instruction including declaration information that identifies a type of …

A processor including a decode unit to receive a vector indexed load plus arithmetic and/or
logical (A/L) operation plus store instruction. The instruction is to indicate a source packed …

According to one embodiment, an occurrence of an instruction is fetched. The instruction's
format specifies its only source operand from a single vector write mask register, and …

Vector processing engines (VPEs) employing format conversion circuitry in data flow paths
between vector data memory and execution units to provide in-flight format-converting of …

According to one technique, a virtual machine generates an object configured to provide
secure access to memory through one or more memory fencing operations. Through the …

William J. Stock (57) ABSTRACT Mechanisms for performing a scattered load operation are
provided. With these mechanisms, an extended address is received in a cache memory of a …

Instructions and logic provide vectorization of conditional loops. A vector expand instruction
has a parameter to specify a source vector, a parameter to specify a conditions mask …