A survey of computer architecture simulation techniques and tools
Computer architecture simulators play an important role in advancing computer architecture
research. With wider research directions and the increased number of simulators that have …
research. With wider research directions and the increased number of simulators that have …
An evaluation of high-level mechanistic core models
Large core counts and complex cache hierarchies are increasing the burden placed on
commonly used simulation and modeling techniques. Although analytical models provide …
commonly used simulation and modeling techniques. Although analytical models provide …
Graphite: A distributed parallel simulator for multicores
This paper introduces the Graphite open-source distributed parallel multicore simulator
infrastructure. Graphite is designed from the ground up for exploration of future multi-core …
infrastructure. Graphite is designed from the ground up for exploration of future multi-core …
Asim: A performance model framework
The longevity and usefulness of a microprocessor performance model has historically
depended on the model writer's skills and discipline. However, at Compaq the models …
depended on the model writer's skills and discipline. However, at Compaq the models …
Mparm: Exploring the multi-processor soc design space with systemc
L Benini, D Bertozzi, A Bogliolo, F Menichelli… - Journal of VLSI signal …, 2005 - Springer
Technology is making the integration of a large number of processors on the same silicon
die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a …
die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a …
JETTY: Filtering snoops for reduced energy consumption in SMP servers
We propose methods for reducing the energy consumed by snoop requests in snoopy bus-
based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops …
based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops …
RAMP gold: an FPGA-based architecture simulator for multiprocessors
We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid
early design-space exploration of manycore systems. The RAMP Gold prototype is a high …
early design-space exploration of manycore systems. The RAMP Gold prototype is a high …
Fast out-of-order processor simulation using memoization
E Schnarr, JR Larus - ACM SIGPLAN Notices, 1998 - dl.acm.org
Our new out-of-order processor simulatol; FastSim, uses two innovations to speed up
simulation 8--15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy …
simulation 8--15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy …
Using prediction to accelerate coherence protocols
SS Mukherjee, MD Hill - Proceedings of the 25th annual international …, 1998 - dl.acm.org
Most large shared-memory multiprocessors use directory protocols to keep per-processor
caches coherent. Some memory references in such systems, however, suffer long latencies …
caches coherent. Some memory references in such systems, however, suffer long latencies …
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research
community needs a dramatic increase in simulation capacity. We believe FPGA Architecture …
community needs a dramatic increase in simulation capacity. We believe FPGA Architecture …