The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …

H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …

Future processors will likely have large on-chip caches with a possibility of dedicating an
entire die for on-chip storage in a 3D stacked design. With the ever growing disparity …

A significant part of future microprocessor real estate will be dedicated to 12 or 13 caches.
These on-chip caches will heavily impact processor performance, power dissipation, and …

To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Buffers in on-chip networks consume significant energy, occupy chip area, and increase
design complexity. In this paper, we make a case for a new approach to designing on-chip …

With the trend towards increasing number of cores in chip multiprocessors, the on-chip
interconnect that connects the cores needs to scale efficiently. In this work, we propose the …

We develop detailed area and energy models for on-chip interconnection networks and
describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using …

On-chip interconnection networks are rapidly becoming a key enabling technology for
commodity multicore processors and SoCs common in consumer embedded systems, the …