The complexity of integrated circuits is continuously increasing, leading to a growing
demand for methodologies that offer comprehensive mixed-signal verification concepts …

Coverage monitoring has become increasingly significant for analog designs considering
the life cycle of analog design IPs that are first designed and verified in isolation and then …

The verification phase carries an important role in design cycle of a System on Chip (SoC). A
verification environment may be prepared using SystemVerilog without using any particular …

This paper presents a verification architecture of the Bluetooth Low Energy Link Layer
Controller. The tested controller is a hardware implementation of the lower layers, described …

As the fabrication technology is advancing more logic is being placed on a silicon die which
makes verification more challenging task than ever. More than 70% of the design cycle is …

Coverage is a key indicator for verification progress, verification closure, and verification
sign-off in an integrated circuit design. The notion of coverage management, namely, the …

An efficient method is presented for automatically locating address block candidates in
images of mail pieces. An image is segmented into clusters and the candidate cluster, based …

The Universal Verification Methodology is a standard which is designed to enable creation
of reusable, robust and interoperable verification IP and testbench components. In this work …

The comparison of analog behavior is still a timeconsuming and error-prone procedure,
which has do be done manually and therefore mainly relies on the expertise of the …

With the conventional directed testbench, it is highly improbably to handle verification of
current complex Integrated Circuit (IC) designs, because a person has to manually create …