A 150-MS/s fully dynamic SAR-assisted pipeline ADC using a floating ring amplifier and gain-enhancing miller negative-C

S Song, T Kang, S Lee, MP Flynn - IEEE Open Journal of the …, 2024 - ieeexplore.ieee.org
This article introduces a fully dynamic SAR-assisted pipeline ADC that uses a floating ring
amplifier (FLORA) and gain-enhancing Miller negative capacitance (Miller negative-C) …

The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs

CH Chan, M Zhang, Y Cao, H Zhao… - 2024 IEEE Custom …, 2024 - ieeexplore.ieee.org
The development of high-speed analog-to-digital converters (ADCs) continues to be driven
by the relentless demand for faster and more precise data conversion across numerous …

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test

Y Huang, G Fu, X Zhang, Y Xiong, Y Zhang, S Liu… - Microelectronics …, 2024 - Elsevier
The built-in self-test (BIST) circuit is designed to be highly integrated with ADC under test
and tests the static linearity based on the stimulus error identification and removal (SEIR) …

An 11-bit 360-MS/s Pipelined SAR ADC With Feedback Factor Compensation Using a Dynamic Negative-C-Assisted Residue Amplifier

Y Kwon, J Won, Y Chae - … on Circuits and Systems I: Regular …, 2024 - ieeexplore.ieee.org
This paper presents an energy-efficient residue amplification for low-power high-speed
pipelined SAR ADC, whose residue amplifier is assisted by a dynamic negative capacitance …

An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier

Y Kwon, S Lee, C Lee, H Yoon, B Min… - 2023 IEEE Asian Solid …, 2023 - ieeexplore.ieee.org
Pipelined SAR ADCs are widely used for moderate-to-high resolution applications. In this
architecture, a residue amplifier plays a key role in speed and linearity, so it is inevitable that …