FPGA architecture: Survey and challenges

I Kuon, R Tessier, J Rose - Foundations and Trends® in …, 2008 - nowpublishers.com
Abstract Field-Programmable Gate Arrays (FPGAs) have become one of the key digital
circuit implementation media over the last decade. A crucial part of their creation lies in their …

A tileable switch module architecture for homogeneous 3D FPGAs

SA Razavi, MS Zamani… - 2009 IEEE International …, 2009 - ieeexplore.ieee.org
3D technology is an attractive solution for reducing wirelength in a field programmable gate
array (FPGA). However, trough silicon vias (TSV) are limited in number. In this paper, we …

Monolithic 3-D FPGAs

Z Zhang, YY Liauw, C Chen… - Proceedings of the …, 2015 - ieeexplore.ieee.org
This paper reviews the recent developments in monolithic 3-D field-programmable gate
arrays (FPGAs). Enabling technologies are covered. Three representative groups of …

Power estimation of embedded multiplier blocks in FPGAs

R Jevtic, C Carreras - IEEE transactions on Very large scale …, 2009 - ieeexplore.ieee.org
The use of embedded multiplier blocks has become a norm in DSP applications due to their
high performance and low power consumption. However, as their implementation details in …

A low-power field-programmable gate array routing fabric

M Lin, A El Gamal - IEEE transactions on very large scale …, 2009 - ieeexplore.ieee.org
This paper describes a new programmable routing fabric for field-programmable gate arrays
(FPGAs). Our results show that an FPGA using this fabric can achieve 1.57 times lower …

VCTA: a via-configurable transistor array regular fabric

M Pons, F Moll, A Rubio, J Abella… - 2010 18th IEEE/IFIP …, 2010 - ieeexplore.ieee.org
Layout regularity is introduced progressively by integrated circuit manufacturers to reduce
the increasing systematic process variations in the deep sub-micron era. In this paper we …

Domain-specific processor with 3d integration for medical image processing

J Cong, K Guruaj, M Huang, S Li… - ASAP 2011-22nd IEEE …, 2011 - ieeexplore.ieee.org
The growth of 3D technology had led to opportunities for stacked multiprocessor-accelerator
computing platforms with high-bandwidth and low-latency TSV connections between them …

High-performance, cost-effective heterogeneous 3D FPGA architectures

R Le, S Reda, RI Bahar - Proceedings of the 19th ACM Great Lakes …, 2009 - dl.acm.org
In this paper, we propose novel architectural and design techniques for three-dimensional
field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop …

Spin-Orbit torque neuromorphic fabrics for low-leakage reconfigurable in-memory computation

M Liu, P Borulkar, M Hossain… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this article, a neural spin-orbit torque (NSOT)-based emerging device technology
reconfigurable fabric is developed and assessed as a low-leakage power alternative to the …

Improving FPGA design with monolithic 3D integration using high dense inter-stack via

SR Srinivasa, K Mohan, WH Chen… - 2017 IEEE Computer …, 2017 - ieeexplore.ieee.org
This paper proposes to use the high density of vias enabled by monolithic 3D integration to
produce multi-stack FPGA designs with improved performance and functionality. The use of …