Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …

Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …

Example implementations are directed to more efficiently delivering a multicast message to
multiple destination components from a source component. Multicast environment is …

The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …

US9569579B1 - Automatic pipelining of NoC channels to meet timing and/or performance -
Google Patents US9569579B1 - Automatic pipelining of NoC channels to meet timing and/or …

A two-phase asynchronous transmission circuit for transmitting data over a wired interface
according to a two-phase asynchronous protocol, the transmission circuit including: N data …

To provide an asynchronous circuit capable of power gating, a semiconductor device is
configured with first to third terminals, a latch circuit, and a memory circuit. The third terminal …

Asynchronous circuits are a promising design style for low-power and high-performance
applications, where asynchronous templates have been widely used to automate the design …

Different example implementations of the present disclosure relates to methods and
computer readable mediums for automatically generating physically aware NoC design and …

Methods and example implementations described herein are generally directed to the
addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance …