[图书][B] Three-dimensional integrated circuit design

VF Pavlidis, I Savidis, EG Friedman - 2017 - books.google.com
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …

[图书][B] An introduction to VLSI physical design

M Sarrafzadeh, CK Wong - 1996 - dl.acm.org
From the Publisher: This text treats the physical design of very large scale integrated circuits
gradually and systematically. It examines the design problem and the design process with …

Interconnect-based design methodologies for three-dimensional integrated circuits

VF Pavlidis, EG Friedman - Proceedings of the IEEE, 2009 - ieeexplore.ieee.org
Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides
achieved in 3-D manufacturing technologies. Advanced design methodologies for two …

Congestion-constrained layer assignment for via minimization in global routing

TH Lee, TC Wang - … Transactions on Computer-Aided Design of …, 2008 - ieeexplore.ieee.org
In this paper, we study the problem of layer assignment for via minimization, which arises
during multilayer global routing. In addressing this problem, we take the total overflow and …

Track assignment: A desirable intermediate step between global routing and detailed routing

S Batterywala, N Shenoy, W Nicholls… - Proceedings of the 2002 …, 2002 - dl.acm.org
Routing is one of the most complex stages in the back-end design process. Simple routing
algorithms based on two stages of global routing and detailed routing do not offer …

Block-level 3-D global routing with an application to 3-D packaging

J Minz, SK Lim - IEEE Transactions on Computer-Aided Design …, 2006 - ieeexplore.ieee.org
Three-dimensional (3-D) packaging via system-on-a-package (SOP) has been recently
proposed as an alternative solution to overcome the limitation of system-on-a-chip (SOC) …

Fast approximation algorithms on maxcut, k-coloring, and k-color ordering for VLSI applications

JD Cho, S Raje, M Sarrafzadeh - IEEE Transactions on …, 1998 - ieeexplore.ieee.org
There are a number of VLSI problems that have a common structure. We investigate such a
structure that leads to a unified approach for three independent VLSI layout problems …

Placement and routing for 3-D system-on-package designs

JM Minz, E Wong, M Pathak… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
Three-dimensional (3-D) packaging via system-on-package (SOP) is a viable alternative to
system-on-chip (SOC) to meet the rigorous requirements of today's mixed signal system …

NEWS: A net-even-wiring system for the routing on a multilayer PGA package

CC Tsai, CM Wang, SJ Chen - IEEE Transactions on Computer …, 1998 - ieeexplore.ieee.org
Given a die with I/O pads wire bonded onto the multilayer substrates of a pin grid array
(PGA) package, a three-step net-even-wiring system (NEWS) is proposed to complete the …

M/sup 2/R: Multilayer routing algorithm for high-performance MCMs

JD Cho, KF Liao, S Raje… - IEEE Transactions on …, 1994 - ieeexplore.ieee.org
We introduce a new multilayer routing strategy for high-performance MCMs whose objective
is to route all nets optimizing routing performance and to satisfy various design constraints …