Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
The challenges and emerging technologies for low-power artificial intelligence IoT systems
L Ye, Z Wang, Y Liu, P Chen, H Li… - … on Circuits and …, 2021 - ieeexplore.ieee.org
The Internet of Things (IoT) is an interface with the physical world that usually operates in
random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips …
random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips …
An energy-efficient comparator with dynamic floating inverter amplifier
This article presents an energy-efficient comparator design. The pre-amplifier adopts an
inverter-based input pair powered by a floating reservoir capacitor; it realizes both current …
inverter-based input pair powered by a floating reservoir capacitor; it realizes both current …
A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise
HS Bindra, CE Lokin, D Schinkel… - IEEE journal of solid …, 2018 - ieeexplore.ieee.org
A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS
process. The dynamic bias with a tail capacitor is simple to implement and ensures that the …
process. The dynamic bias with a tail capacitor is simple to implement and ensures that the …
The design of a comparator [the analog mind]
B Razavi - IEEE Solid-State Circuits Magazine, 2020 - ieeexplore.ieee.org
Nyquist-rate and oversampling analog-to-digital converters (ADCs) incorporate comparators
to perform quantization and possibly sampling. Comparators thus have a significant impact …
to perform quantization and possibly sampling. Comparators thus have a significant impact …
First demonstration of in-memory computing crossbar using multi-level Cell FeFET
Advancements in AI led to the emergence of in-memory-computing architectures as a
promising solution for the associated computing and memory challenges. This study …
promising solution for the associated computing and memory challenges. This study …
Power-saving design opportunities for wireless intracortical brain–computer interfaces
The efficacy of wireless intracortical brain–computer interfaces (iBCIs) is limited in part by
the number of recording channels, which is constrained by the power budget of the …
the number of recording channels, which is constrained by the power budget of the …
112-Gb/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels
Y Krupnik, Y Perelman, I Levin… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer
transceiver (SERDES) receiver is implemented on Intel's 10-nm FinFET process. The …
transceiver (SERDES) receiver is implemented on Intel's 10-nm FinFET process. The …
A 0.5 V 55 64 2 Channel Binaural Silicon Cochlea for Event-Driven Stereo-Audio Sensing
M Yang, CH Chien, T Delbruck… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
This paper presents a 64× 2 channel stereo-audio sensing front end with parallel
asynchronous event output inspired by the biological cochlea. Each binaural channel …
asynchronous event output inspired by the biological cochlea. Each binaural channel …
Interference robust detector-first near-zero power wake-up receiver
This paper presents the development of a wake-up receiver (WuRX) at nanowatt power
levels for event-driven applications. This paper improves the state of the art, obtaining higher …
levels for event-driven applications. This paper improves the state of the art, obtaining higher …