Analog design with Line-TFET device experimental data: from device to circuit level

W Gonçalez Filho, E Simoen… - Semiconductor …, 2020 - iopscience.iop.org
This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog
applications. It presents the DC and small signal characteristics of these devices and …

Modified GRNN based atomic modeling approach for nanoscale devices and TFET implementation

AÖ Polat, M Avcı - Materials Today Communications, 2021 - Elsevier
The simulation of realistic device models in quantum transport requires an extreme amount
of memory and computation time. The computational burden in quantum transport is caused …

Operational transconductance amplifier designed with nanowire tunnel-FET with Si, SiGe and Ge sources using experimental data

A de Moraes Nogueira, PG Der Agopian… - Semiconductor …, 2020 - iopscience.iop.org
In this paper operational transconductance amplifiers (OTA) were designed with nanowire
(NW) tunnel field effect transistors (TFET) with different source materials (Si, SiGe, and Ge) …

Silicon nanowire Tunnel-FET differential amplifier using Verilog-A lookup table approach

AM Nogueira, PGD Agopian… - 2019 34th Symposium on …, 2019 - ieeexplore.ieee.org
Electrical characterization of a silicon nanowire Tunnel Field Effect Transistor (TFET) is used
to construct a lookup table in order to model and simulate analog circuit through Verilog-A …

Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs

AM Nogueira, PGD Agopian, E Simoen… - Solid-State …, 2021 - Elsevier
Abstract An Operational Transconductance Amplifier (OTA) designed with SiGe-source
nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire …

Investigation of interface trap charges and temperature on RF performance with noise analysis for IoT application of a heterojunction tunnel FET

D Das, U Chakraborty - Internet of Things and Data Mining for …, 2022 - api.taylorfrancis.com
In the recent past, the CMOS technology has been unceasingly scaled down in order to
shrink the device dimensions to the extent of a nanometre regime to enhance the overall …

Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance

H Simhadri, SS Dan, R Yadav… - International Journal of …, 2021 - Wiley Online Library
This paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device
optimized for superior analog performance. DGLTFET has thrice the on currents I on, at least …

14 Investigation of Interface Trap

HT FET, D Das, U Chakraborty - … of Things and Data Mining for …, 2022 - books.google.com
In the recent past, the CMOS technology has been unceasingly scaled down in order to
shrink the device dimensions to the extent of a nanometre regime to enhance the overall …

Experimental behavior of Line-TFET applied to Low-Dropout Voltage Regulator

W de Lima Silva, PG Der Agopian… - 2022 36th Symposium …, 2022 - ieeexplore.ieee.org
This work presents the design of Low Dropout Voltage Regulator (LDO) with Line-Tunnel
Field Effect Transistor (Line-TFET), in which the transistor was modeled using Verilog-A and …

Experimental silicon tunnel-FET device model applied to design a Gm-C filter

RS Rangel, PGD Agopian… - … Science and Technology, 2020 - iopscience.iop.org
This work presents the design of a Gm-C filter using experimental data of a silicon tunneling
field effect transistors (TFET) device. The application takes advantage of the low gm of a Si …