An energy efficient multi-retention STT-MRAM memory architecture for IoT applications
B Jahannia, SA Ghasemi… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This brief proposes a novel energy-optimized multi-retention STT-MRAM architecture for IoT
devices that addresses the limitations of the traditional memory architecture consisting of …
devices that addresses the limitations of the traditional memory architecture consisting of …
A high‐capacity and nonvolatile spintronic associative memory hardware accelerator
M Rezaei, A Amirany, MH Moaiyeri… - IET Circuits, Devices & …, 2023 - Wiley Online Library
Significant progress has been made in manufacturing emerging technologies in recent
years. This progress implemented in‐memory‐computing and neural networks, one of …
years. This progress implemented in‐memory‐computing and neural networks, one of …
A design space exploration and evaluation for main-memory hash joins in storage class memory
In this paper, we seek to perform a rigorous experimental study of main-memory hash joins
in storage class memory (SCM). In particular, we perform a design space exploration in real …
in storage class memory (SCM). In particular, we perform a design space exploration in real …
Low-cost and variation-aware spintronic ternary random number generator
In this paper, a ternary true random number generator (TTRNG) is designed and simulated
using the stochastic behavior of the magnetic tunnel junction (MTJ) device at currents lower …
using the stochastic behavior of the magnetic tunnel junction (MTJ) device at currents lower …
Load Balanced PIM-Based Graph Processing
X Zhao, S Chen, Y Kang - ACM Transactions on Design Automation of …, 2024 - dl.acm.org
Graph processing is widely used for many modern applications, such as social networks,
recommendation systems, and knowledge graphs. However, processing large-scale graphs …
recommendation systems, and knowledge graphs. However, processing large-scale graphs …
On the design of power attack immune spintronic associative memory
The growing utilization of neural networks has led to a heightened focus on the hardware
implementation of such networks. Security concerns associated with these implementations …
implementation of such networks. Security concerns associated with these implementations …
CRPIM: An efficient compute-reuse scheme for ReRAM-based Processing-in-Memory DNN accelerators
S Hong, YC Chung - Journal of Systems Architecture, 2024 - Elsevier
Resistive random access memory (ReRAM) is a promising technology for AI Processing-in-
Memory (PIM) hardware because of its compatibility with CMOS, small footprint, and ability …
Memory (PIM) hardware because of its compatibility with CMOS, small footprint, and ability …
Improving energy efficiency and fault tolerance of mission-critical cloud task scheduling: A mixed-integer linear programming approach
Cloud services have become indispensable in critical sectors such as healthcare, drones,
digital twins, and autonomous vehicles, providing essential infrastructure for data processing …
digital twins, and autonomous vehicles, providing essential infrastructure for data processing …
An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators
A Dorostkar, H Farbeh… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) accelerator
is a promising platform for processing massively memory intensive matrix-vector …
is a promising platform for processing massively memory intensive matrix-vector …
SPLIM: Bridging the Gap Between Unstructured SpGEMM and Structured In-situ Computing
Sparse matrix-matrix multiplication (SpGEMM) is a critical kernel widely employed in
machine learning and graph algorithms. However, high sparsity of real-world matrices …
machine learning and graph algorithms. However, high sparsity of real-world matrices …