Monolithic 3D ICs (M3D) are fabricated using a sequential process that grows new device
and interconnect tiers in a bottom-up fashion. This fabrication process is in contrast to …

This paper focuses on low-power and low-slew clock network design and analysis for
through-silicon via (TSV) based three-dimensional stacked ICs (3D ICs). First, we investigate …

Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D
integration technology emerges as a viable option to improve chip performance and …

Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …

Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D
interconnections to realize considerable high-bandwidth throughput in vertically stacked and …

The adoption of three-dimensional (3D) integration has revolutionized NAND flash memory
technology, and a similar transformative potential exists for logic circuits, by stacking …

Pre-bond testing of 3D stacked ICs involves testing individual dies before bonding. The
overall yield of 3D ICs improves with prebond testability because designers can avoid …

Purpose This paper aims to present a process to generate physics-based trade-off curves
(ToCs) to facilitate lean product development processes by enabling two key activities of set …

In 3D VLSI, through-silicon vias (TSVs) are relatively large, and closely spaced. This results
in a situation in which noise on one or more TSVs may deteriorate the delay and signal …

Three-dimensional (3D) integration is an important technology that addresses fundamental
limitations of on-chip interconnects. Several design issues related to 3D circuits, such as …