Investigation of junctionless fin-FET characterization in deep cryogenic temperature: DC and RF analysis

D Madadi - IEEE Access, 2022 - ieeexplore.ieee.org
This work presents the SOI Junctionless Fin-FET characterization in Deep Cryogenic
behavior (DC-JLFET). Results show that the JLT device is well-suited for various operations …

Junction-less SOI FET with an Embedded p+ Layer: Investigation of DC, RF, and Negative Capacitance Characteristics

D Madadi, S Mohammadi - Silicon, 2023 - Springer
This paper presents a Junction-less SOI FET with an embedded p+ layer (EP-JLFET) to
obtain extensive volume depletion in 14 nm channel length of the device. The p+ embedded …

500 V breakdown voltage in β‐Ga2O3 laterally diffused metal‐oxide‐semiconductor field‐effect transistor with 108 MW/cm2 power figure of merit

N Abedi Rik, AA Orouji, D Madadi - IET Circuits, Devices & …, 2023 - Wiley Online Library
The authors' present a silicon‐on‐insulator (SOI) laterally diffused metal‐oxide‐
semiconductor field‐effect transistor (LDMOSFET) with β‐Ga2O3, which is a large bandgap …

Pyramid P+ area in SOI junction-less MOSFET for logic applications: DC investigation

M Bolokian, AA Orouji, A Abbasi, M Houshmand - Applied Nanoscience, 2023 - Springer
This work presents silicon-on-insulator (SOI) junction-less FETs (C-JLFET) with a pyramid
P+ area within the buried oxide region (PP-JLFET). The Silvaco software analysis shows …

Successful electric field modulation to enhance DC and RF features in SOI LDMOS transistors using a β-Ga2O3 film

A Sohrabi-Movahed, AA Orouji - Journal of Materials Science: Materials in …, 2024 - Springer
In this paper, a successful electric field modulation in Lateral Double-diffused Metal Oxide
Semiconductor (LDMOS) transistors to enhance the electrical characteristics is presented. A …

4H-SiC layer with multiple trenches in lateral double-diffused metal-oxide-semiconductor transistors for high temperature and high voltage applications

A Sohrabi-Movahed, AA Orouji - … of Vacuum Science & Technology B, 2023 - pubs.aip.org
In this paper, we present a novel lateral double-diffused metal-oxide-semiconductor
(LDMOS) transistor for high-temperature and high breakdown voltage applications. The key …

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

KM Abrishami, AA Orouji, D Madadi - Physica Scripta, 2023 - iopscience.iop.org
This work uses a superior depletion technique to present a junctionless silicon-on-insulator
(SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested …

Off‐State Current Improvement of Double‐Gate Junctionless Field‐Effect Transistor by Modifying Central Potential

KM Abrishami, AA Orouji - physica status solidi (a), 2023 - Wiley Online Library
This work presents a double‐gate junctionless metal‐oxide field‐effect transistor (JLT) in a
20 nm regime by modifying central potential. In the proposed device, the off‐state current is …

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High …

J Singh, RK Chauhan - physica status solidi (a), 2023 - Wiley Online Library
Junctionless metal–oxide‐semiconductor field‐effect transistors (MOSFETs) have emerged
as a promising alternative to conventional MOSFETs, offering simplified fabrication and …

A Modulation Electric Field Technique to Improve the LD-MOSFET Performance with a P-type Ga2O3 Pocket

SMH Jafari, AA Orouji, D Madadi - Silicon, 2023 - Springer
This study presents a modulation technique of electric field to improve the electrical
performances of silicon-on-insulator (SOI) laterally diffused metal–oxide–semiconductor …