Digital Multiplier is the important part of ALU and many other arithmetic operations. VLSI
designers show keen interest in optimizing area, power and delay in multiplier. In this paper …

Various “arithmetic operations”,“signal and image processing systems” and “communication
devices” incorporate multipliers as the basic element. Vedic mathematics is an ancient …

In this paper, a novel Vedic multiplier based on binary coded decimal (BCD) technique is
introduced. The results of multiplication of two 4-bit numbers are listed in columns in order to …

In this computer era, it is very important to optimize and improve the efficiency of VLSI design
circuits for area, speed and power dissipation. To increase speed and decrease power …

In this paper, the structure of a 16-by-16 unsigned hybrid (serial-parallel) multiplier has been
proposed. Parallel multipliers, in comparison with serial multipliers, have higher speed and …

The 8 bit computational engines are superseded by 32 bit core. The 32 bit core is highly
dense and available in smaller size as compared to earlier 8 bit cores thanks to …

The processors used in the electronic devices spend more time on multiplication operation
compared to other arithmetic operations like addition and subtraction. Generally, multiplying …

This paper presents a high-performance multiplier based on 4× 1 multiplexer. The 4× 1
multiplexer is defined as a combinational logic circuit. It is used to select one of four digital …

Shodhganga@INFLIBNET: Vedic Mathematics Based Hardware Optimization for Various Arithmetic
Skip navigation DSpace logo Home Browse Universities & Departments Browse by : Upload Date …