A comparison of FPGA and GPU for real-time phase-based optical flow, stereo, and local image features

K Pauwels, M Tomasi, JD Alonso, E Ros… - IEEE Transactions …, 2011 - ieeexplore.ieee.org
Low-level computer vision algorithms have extreme computational requirements. In this
work, we compare two real-time architectures developed using FPGA and GPU devices for …

Parallel architecture for hierarchical optical flow estimation based on FPGA

F Barranco, M Tomasi, J Diaz… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
The proposed work presents a highly parallel architecture for motion estimation. Our system
implements the well-known Lucas and Kanade algorithm with the multi-scale extension for …

An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA

Y Yan, Y Ling, K Huang, G Chen - Journal of Systems Architecture, 2023 - Elsevier
Recently, accelerator architectures of deep neural networks (DNNs) have been designed to
accelerate computer vision tasks, gaining the advantages of both accuracy and speed …

A real-time and efficient optical flow tracking accelerator on fpga platform

Y Gong, J Zhang, X Liu, J Li, Y Lei… - … on Circuits and …, 2023 - ieeexplore.ieee.org
Optical flow is a highly efficient visual tracking algorithm, which is commonly used to
estimate pixel movement between two consecutive images in a video sequence. However …

FPGA-based hardware implementation of real-time optical flow calculation

K Seyid, A Richaud, R Capoccia… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Optical flow calculation algorithms are hard to implement on the hardware level in real-time,
due to their complexity and high computational load. Therefore, presented works in the …

Efficient hardware implementation of the Horn-Schunck algorithm for high-resolution real-time dense optical flow sensor

M Komorkiewicz, T Kryjak, M Gorgon - Sensors, 2014 - mdpi.com
This article presents an efficient hardware implementation of the Horn-Schunck algorithm
that can be used in an embedded optical flow sensor. An architecture is proposed, that …

FPGA Acceleration of the Horn and Schunck Hierarchical algorithm

I Bournias, R Chotin… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
This work proposes a highly tunable motion estimation architecture. We implement the Horn
and Schunck algorithm with the hierarchical extension for larger motion estimations in …

Massive parallel-hardware architecture for multiscale stereo, optical flow and image-structure computation

M Tomasi, M Vanegas, F Barranco… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
Low-level vision tasks pose an outstanding challenge in terms of computational effort: pixel-
wise operations require high-performance architectures to achieve real-time processing …

Real-time architecture for a robust multi-scale stereo engine on FPGA

M Tomasi, M Vanegas, F Barranco… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
In this work, we present a real-time implementation of a stereo algorithm on field-
programmable gate array (FPGA). The approach is a phase-based model that allows …

Flowacc: Real-time high-accuracy dnn-based optical flow accelerator in fpga

Y Ling, Y Yan, K Huang, G Chen - 2022 Design, Automation & …, 2022 - ieeexplore.ieee.org
Recently, accelerator architectures have been designed to use deep neural networks
(DNNs) to accelerate computer vision tasks, possessing the advantages of both accuracy …