Design of an energy-efficient CMOS-compatible NoC architecture with millimeter-wave wireless interconnects
The Network-on-chip (NoC) is an enabling technology to integrate large numbers of
embedded cores on a single die. The existing methods of implementing a NoC with planar …
embedded cores on a single die. The existing methods of implementing a NoC with planar …
Performance evaluation and design trade-offs for wireless network-on-chip architectures
Massive levels of integration are making modern multicore chips all pervasive in several
domains. High performance, robustness, and energy-efficiency are crucial for the …
domains. High performance, robustness, and energy-efficiency are crucial for the …
A 1.2-pJ/bit 16-Gb/s 60-GHz OOK transmitter in 65-nm CMOS for wireless network-on-chip
This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed
for wireless network-on-chip applications. Aiming at an intra-chip communication distance of …
for wireless network-on-chip applications. Aiming at an intra-chip communication distance of …
An 18.7-Gb/s 60-GHz OOK demodulator in 65-nm CMOS for wireless network-on-chip
This paper presents a high-efficiency 60-GHz on-off keying (OOK) demodulator for high-
speed short-range wireless communications such as wireless network-on-chip (WiNoC) …
speed short-range wireless communications such as wireless network-on-chip (WiNoC) …
A resilient 2-D waveguide communication fabric for hybrid wired-wireless NoC design
Hybrid wired-wireless Network-on-Chip (WiNoC) has emerged as an alternative solution to
the poor scalability and performance issues of conventional wireline NoC design for future …
the poor scalability and performance issues of conventional wireline NoC design for future …
Design space exploration for wireless NoCs incorporating irregular network routing
The millimeter-wave small-world wireless network-on-chip (mSWNoC) is an enabling
interconnect architecture to design high-performance and low-power multicore chips. As the …
interconnect architecture to design high-performance and low-power multicore chips. As the …
Monopoles loaded with 3-D-printed dielectrics for future wireless intrachip communications
J Wu, AK Kodi, S Kaya, A Louri… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
We propose a novel antenna design enabled by 3-D printing technology for future wireless
intrachip interconnects aiming at applications of multicore architectures and system-on …
intrachip interconnects aiming at applications of multicore architectures and system-on …
A wideband body-enabled millimeter-wave transceiver for wireless network-on-chip
A highly energy-efficient on-chip communication network is crucial for the development of
future multi-core chips. In this paper, a wideband millimeter-wave (mm-wave) transceiver …
future multi-core chips. In this paper, a wideband millimeter-wave (mm-wave) transceiver …
Wireless network-on-chip: a new era in multi-core chip design
The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of
embedded cores on a single die. The existing method of implementing a NoC with planar …
embedded cores on a single die. The existing method of implementing a NoC with planar …
A 16-Gb/s low-power inductorless wideband gain-boosted baseband amplifier with skewed differential topology for wireless network-on-chip
This paper presents an inductorless wideband gain-boosted baseband (BB) amplifier
suitable for wireless network-on-chip (WiNoC) architectures. Current reuse active feedback …
suitable for wireless network-on-chip (WiNoC) architectures. Current reuse active feedback …