All-digital PLL and transmitter for mobile phones
RB Staszewski, JL Wallberg, S Rezeq… - IEEE journal of Solid …, 2005 - ieeexplore.ieee.org
We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a
single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The …
single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The …
[图书][B] All-digital frequency synthesizer in deep-submicron CMOS
RB Staszewski, PT Balsara - 2006 - books.google.com
A new and innovative paradigm for RF frequency synthesis and wireless transmitter design
Learn the techniques for designing and implementing an all-digital RF frequency …
Learn the techniques for designing and implementing an all-digital RF frequency …
[图书][B] Sinusoidal oscillators and waveform generators using modern electronic circuit building blocks
Sinusoidal oscillators and waveform generators have numerous applications in electronics,
instrumentation, measurement, communications, control systems, and signal processing …
instrumentation, measurement, communications, control systems, and signal processing …
A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones
RB Staszewski, CM Hung, N Barton… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver …
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver …
A spectral model for RF oscillators with power-law phase noise
In this paper, we apply correlation theory methods to obtain a model for the near-carrier
oscillator power-spectral density (PSD). Based on the measurement-driven representation of …
oscillator power-spectral density (PSD). Based on the measurement-driven representation of …
Multirate timestamp modeling for ultralow-jitter frequency synthesis: A tutorial
Y Hu, T Siriburanon… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this tutorial brief, we introduce a unified wideband phase-noise theory framework of
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
A charge-sharing locking technique with a general phase noise theory of injection locking
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
Understanding phase error and jitter: Definitions, implications, simulations, and measurement
I Galton, C Weltin-Wu - … Transactions on Circuits and Systems I …, 2018 - ieeexplore.ieee.org
Precision oscillators are ubiquitous in modern electronic systems, and their accuracy often
limits the performance of such systems. Hence, a deep understanding of how oscillator …
limits the performance of such systems. Hence, a deep understanding of how oscillator …
State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS
RB Staszewski - IEEE Transactions on Circuits and Systems I …, 2011 - ieeexplore.ieee.org
The past several years have successfully brought all-digital techniques to the RF frequency
synthesis, which could arguably be considered one of the last strong bastions of the …
synthesis, which could arguably be considered one of the last strong bastions of the …
A 0.3–1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller
DS Kim, H Song, T Kim, S Kim… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
A 0.3–1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller
(ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The …
(ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The …