Approximate Computing: Concepts, Architectures, Challenges, Applications, and Future Directions
AM Dalloo, AJ Humaidi, AK Al Mhdawi… - IEEE …, 2024 - ieeexplore.ieee.org
The unprecedented progress in computational technologies led to a substantial proliferation
of artificial intelligence applications, notably in the era of big data and IoT devices. In the …
of artificial intelligence applications, notably in the era of big data and IoT devices. In the …
Approximating behavioral HW accelerators through selective partial extractions onto synthesizable predictive models
S Xu, BC Schafer - 2019 IEEE/ACM International Conference …, 2019 - ieeexplore.ieee.org
This work presents a method to selectively extract portions of a behavioral description to be
synthesized as a hardware accelerator using High-Level Synthesis (HLS) onto different …
synthesized as a hardware accelerator using High-Level Synthesis (HLS) onto different …
A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing
Low-voltage computing effectively saves energy in circuit operations, but it suffers from an
increasing propagation delay. Approximate computing can significantly reduce the …
increasing propagation delay. Approximate computing can significantly reduce the …
Integrating constraint awareness and multiple approximation techniques in high-level synthesis for fpgas
MT Leipnitz - 2022 - lume.ufrgs.br
The adoption of High-Level Synthesis (HLS) targeting Field-Programmable Gate Arrays
(FPGAs) has increased as the latest HLS tools have evolved to provide high-quality re sults …
(FPGAs) has increased as the latest HLS tools have evolved to provide high-quality re sults …
On the design of high performance hw accelerator through high-level synthesis scheduling approximations
S Xu, BC Schafer - 2020 Design, Automation & Test in Europe …, 2020 - ieeexplore.ieee.org
High-level synthesis (HLS) takes as input a behavioral description (eg C/C++) and
generates efficient hardware through three main steps: allocation, scheduling, and binding …
generates efficient hardware through three main steps: allocation, scheduling, and binding …
Tolerating aging-induced timing violations via configurable approximations
T Sato, T Ukezono - 2019 IEEE 8th Global Conference on …, 2019 - ieeexplore.ieee.org
This paper proposes a technique that increases the lifetime of consumer electronics devices.
As semiconductor technology improves in miniaturizing transistors, aging effect due to Bias …
As semiconductor technology improves in miniaturizing transistors, aging effect due to Bias …
Exploiting configurable approximations for tolerating aging-induced timing violations
T Sato, T Ukezono - IEICE Transactions on Fundamentals of …, 2020 - search.ieice.org
This paper proposes a technique that increases the lifetime of large scale integration (LSI)
devices. As semiconductor technology improves at miniaturizing transistors, aging effects …
devices. As semiconductor technology improves at miniaturizing transistors, aging effects …
From Single Component to System Level Approximate Computing
P Chowdhury - 2022 - utd-ir.tdl.org
Abstract Most Integrated Circuits (ICs) are now heterogeneous Systems-on-Chip (SoC) that
contain a variety of hardware accelerators. These dedicated accelerators execute …
contain a variety of hardware accelerators. These dedicated accelerators execute …
[图书][B] Towards Robust Approximate Computing
S Xu - 2019 - search.proquest.com
Many classes of applications exhibit significant tolerance to inaccuracies in their
computations. Some examples include image processing, multimedia applications, and …
computations. Some examples include image processing, multimedia applications, and …