Process variations have become a critical issue influencing the performance of nanometer
digital circuits at gigascale integration; variations are classified in two types: inter-die and …

One of the factors now beginning to seriously limit clock rates in large synchronous designs
is manufacturing variations in device parameters. Moreover, such random process variations …

The amount of physical variation among electronic components on a die is increasing
rapidly. There is a need for a better understanding of variations in transient fault …

In this paper, an architectural framework for post-silicon tuning of nanoscale CMOS circuits
is developed. The tuning methodology is driven by a¿ tunable¿ gate design that allows the …

In the last two decades, VLSI technology scaling has spurred a rapid growth in the
semiconductor industry. With CMOS device dimensions falling below 100 nm, achieving …

The successful pursuit of the Moore's-law in the semiconductor industry has enabled the
integration of highly complex functionalities on a single chip, thus enabling the proliferation …

We introduce a new methodology for post-silicon characterization of the gate-level variations
in a manufactured Integrated Circuit (IC). The estimated characteristics are based on the …

VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With
CMOS device dimensions falling below 100 nm, achieving higher performance and packing …

Genetic programming is based on the Darwinian evolutionary theory that suggests that the
best solution for a problem can be evolved by populating the solution space with an initial …