Needle guards
RC Sircom, DJ French - US Patent 7,513,888, 2009 - Google Patents
A needle guard (1) based upon a canting plate (6) becomes lockingly engaged with the
needle (2) shaft both upon retraction of the needle tip within the guard (1), and upon any …
needle (2) shaft both upon retraction of the needle tip within the guard (1), and upon any …
Microprocessor with arm and X86 instruction length decoders
GG Henry, T Parks, RE Hooker - US Patent 9,898,291, 2018 - Google Patents
A microprocessor natively translates and executes instructions of both the x86 instruction set
architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter …
architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter …
Apparatus with reduced hardware register set
SJ Craske - US Patent App. 15/222,994, 2017 - Google Patents
An apparatus comprises processing circuitry for processing program instructions according
to a predetermined architec ture defining a number of architectural registers accessible in …
to a predetermined architec ture defining a number of architectural registers accessible in …
Data cache rollbacks for failed speculative traces with memory operations
JG Favor, PG Chan, GR Murphy… - US Patent 8,370,609, 2013 - Google Patents
2008-04-23 Assigned to MONTALVO SYSTEMS, INC. reassignment MONTALVO
SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
Memory ordering queue/versioning cache circuit
JG Favor, PG Chan, GR Murphy… - US Patent 8,024,522, 2011 - Google Patents
2008-04-23 Assigned to MONTALVO SYSTEMS, INC. reassignment MONTALVO
SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
SYSTEMS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources
M Loktyukhin, R Valentine, JC Horn… - US Patent …, 2018 - Google Patents
Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test
functionality on multiple test sources. Some embodiments include fetching instructions, said …
functionality on multiple test sources. Some embodiments include fetching instructions, said …
Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
MJ Ebersole - US Patent 9,336,180, 2016 - Google Patents
(57) ABSTRACT A microprocessor includes hardware registers that instantiate the IA-32
Architecture EDX and EAX GPRS and hardware registers that instantiate the Intel 64 …
Architecture EDX and EAX GPRS and hardware registers that instantiate the Intel 64 …
Hardware apparatuses and methods to fuse instructions
PP Lai, TN Sondag, S Winkel, P Xekalakis… - US Patent …, 2019 - Google Patents
Methods and apparatuses relating to a fusion manager to fuse instructions are described. In
one embodiment, a hardware processor includes a hardware binary translator to translate …
one embodiment, a hardware processor includes a hardware binary translator to translate …
Abort prioritization in a trace-based processor
CP Nelson, JG Favor, RW Thaik - US Patent 7,870,369, 2011 - Google Patents
A method of determining a reason for a trace to be aborted includes receiving at least two
incoming indications of occurrences of abort triggers stemming from the execution of at least …
incoming indications of occurrences of abort triggers stemming from the execution of at least …
Representing a plurality of instructions with a fewer number of micro-operations
R Valentine, I Anati, Z Sperber, I Ouziel… - US Patent …, 2011 - Google Patents
BACKGROUND In typical high-performance, SuperScalar microprocessors, one technique
to improve performance is to reduce the num ber of micro-operations (“uops') to perform …
to improve performance is to reduce the num ber of micro-operations (“uops') to perform …