This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture
where groups of fundamentally independent cores can dynamically morph into a larger …

Clustering is an effective microarchitectural technique for reducing the impact of wire delays,
the complexity, and the power requirements of microprocessors. In this work, we investigate …

Power and complexity issues have led the microprocessor industry to shift to Chip
Multiprocessors in order to be able to better utilize the additional transistors ensured by …

Cache memories are commonly implemented through multiple memory banks to improve
bandwidth and latency. The early knowledge of the data cache bank that an instruction will …

As part of Arizona State University's (ASU) K-12 outreach effort to increase the number of
qualified minority students entering the College of Engineering and Applied Sciences …

Whereas clustered microarchitectures themselves have been extensively studied, the
memory units for these clustered microarchitectures have received relatively little attention …

For the last 30 years, the microprocessor industry has relied on instruction-level parallelism
(ILP) and aggressive clock scaling to translate Moore's Law into exponential performance …

Power constraints led to the end of exponential growth in single–processor performance,
which characterized the semiconductor industry for many years. Single–chip …

This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture
where groups of fundamentally independent cores can dynamically morph into a larger …

Chip multiprocessors (CMPs) hold the prospect of translating Moore's Law into sustained
performance growth by incorporating more and more cores on the die. In the short term, on …