Modeling of crosstalk in through silicon vias
AE Engin, SR Narasimhan - IEEE transactions on …, 2012 - ieeexplore.ieee.org
This paper presents analytical formulas to extract an equivalent circuit model for coupled
through silicon via (TSV) structures in a 3-D integrated circuit. We make use of a …
through silicon via (TSV) structures in a 3-D integrated circuit. We make use of a …
Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip
Reliability is one of the most challenging problems in the context of three-dimensional
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
Thermal-aware high-frequency characterization of large-scale through-silicon-via structures
T Lu, JM Jin - IEEE Transactions on Components, Packaging …, 2014 - ieeexplore.ieee.org
The 3-D integration exacerbates the thermal issues over a single die due to the high-power
density and poor thermal conductivity of the adhesive layers in between the stackedup dies …
density and poor thermal conductivity of the adhesive layers in between the stackedup dies …
Fault-Tolerant 3D-NoC architecture and design: recent advances and challenges
In this paper, we survey recent research work in the design of fault-tolerant three-
dimensional (3D) network-on-chip (NoC), which has drawn lots of research attention from …
dimensional (3D) network-on-chip (NoC), which has drawn lots of research attention from …
Built-in self-test and fault localization for inter-layer vias in monolithic 3D ICs
Monolithic 3D (M3D) integration provides massive vertical integration through the use of
nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling …
nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling …
Efficient analysis of metallic and dielectric posts in parallel-plate waveguide structures
A mode-matching method is proposed for the accurate and fast analysis of structures
composed by metallic and dielectric posts in a parallel-plate waveguide environment. The …
composed by metallic and dielectric posts in a parallel-plate waveguide environment. The …
An efficient hybrid finite-element analysis of multiple vias sharing the same anti-pad in an arbitrarily shaped parallel-plate pair
A hybrid 3-D and equivalent 2-D finite-element method (FEM) is proposed for signal/power
integrity analysis of multiple vias in a shared anti-pad in an arbitrarily shaped parallel-plate …
integrity analysis of multiple vias in a shared anti-pad in an arbitrarily shaped parallel-plate …
Capacitive and inductive tsv-to-tsv resilient approaches for 3d ics
PM Yaghini, A Eghbal, SS Yazdi… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-
dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in …
dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in …
Novel RDL design of wafer-level packaging for signal/power integrity in LPDDR4 application
KB Wu, TY Kuo, CC Hung, B Lin… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
The emerging wafer-level packaging (WLP) technology suffers from serious signal integrity
(SI) and power integrity (PI) issues due to its redistribution layer (RDL). There exhibit serious …
(SI) and power integrity (PI) issues due to its redistribution layer (RDL). There exhibit serious …
Analytical reliability analysis of 3D NoC under TSV failure
The network-on-chip (NoC) technology allows for integration of a manycore design on a
single chip for higher efficiency and scalability. Three-dimensional (3D) NoCs offer several …
single chip for higher efficiency and scalability. Three-dimensional (3D) NoCs offer several …