Cryogenic-aware forward body biasing in bulk CMOS
RWJ Overwater, M Babaie… - IEEE Electron Device …, 2023 - ieeexplore.ieee.org
Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-
voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in …
voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in …
[HTML][HTML] Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications
The development of large-scale quantum computing has boosted an urgent desire for the
advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for …
advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for …
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing
This paper presents a floating inverter amplifier (FIA) that performs high-linearity
amplification and sampling while driving a time-interleaved (TI) SAR ADC, operating from …
amplification and sampling while driving a time-interleaved (TI) SAR ADC, operating from …
A 40 nm Cryo-CMOS Homodyne-Demodulation Readout SoC for Superconducting Qubits
D Minn, K Kang, J Lee, S Bae, B Kim… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This paper presents a cryo-CMOS readout SoC based on a homodyne demodulation
architecture with an integrating receiver. The homodyne receiver module for each qubit …
architecture with an integrating receiver. The homodyne receiver module for each qubit …
Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate Parametric Amplification
In quantum computers, the quantum state discrimination of the physical quantum bits
(Qubits) occupies~ 80% of the quantum error correction (QEC) cycle. The RF reflectometry …
(Qubits) occupies~ 80% of the quantum error correction (QEC) cycle. The RF reflectometry …
A 7-10b Programmable Cryo-CMOS TI-SAR ADC for Multichannel Qubit Readout with On-Chip Background Inter-Channel Mismatch Calibrations
This paper presents a cryo-CMOS dynamic-precision time-interleaved (TI) SAR ADC for
FDM-based qubit readout. The ADC includes on-chip background calibration engines to …
FDM-based qubit readout. The ADC includes on-chip background calibration engines to …
A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator
CW Pai, K Uchida, M Tada, H Ishikuro - Microelectronics Journal, 2024 - Elsevier
This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode
variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme …
variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme …
Investigation of long channel bulk MOSFETs threshold voltage model down to 10 mK and key analog parameters at 4 K
H Su, Y Cai, Y Lin, Y Xie, Y Mai, S Zhou… - … Journal of Numerical …, 2024 - Wiley Online Library
Threshold voltage behavior at cryogenic temperatures is dominated by interface traps. This
mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward …
mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward …
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction
Cryogenic Complementary Metal Oxide Semiconductor (CMOS) circuitry is inevitable to
drive and read out qubits for the realization of scalable Quantum Computers (QCs). Analog …
drive and read out qubits for the realization of scalable Quantum Computers (QCs). Analog …
A 10 MS/s 12-bit Cryogenic SAR ADC in 22nm FD SOI for Quantum Computing
This paper presents a 12-bit cryogenic successive-approximation (SAR) ADC designed in
22nm FD SOI technology for quantum computing. An auto-zeroing technique and dual …
22nm FD SOI technology for quantum computing. An auto-zeroing technique and dual …