Aggressive scaling technology in deep sub-micron System-on-Chip (SoC) design brings
various challenges to the Integrated Circuits (IC) designers. The significant challenges are …

An efficient technique for mapping application tasks to heterogeneous processing elements
(PEs) on a network-on-chip (NoC) platform, operating at multiple voltage levels, is presented …

In this paper, we propose an SKB-tree representation for two modern floorplaning problems:
fixed-outline and voltage-island driven floorplanning. Since SKB-tree can dynamically …

Power optimization is a crucial concern for modem circuit designs. Multiple supply voltages
(MSV's) provide an effective technique for the power optimization. This paper addresses the …

Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in
the power consumption of processors; however, the lower the voltage, the higher the …

An energy-quality scalable coarse grain reconfigurable architecture (CGRA) based on the
voltage overscaling (VOS) technique is presented. The approximation level of each …

Energy efficiency has become a very important issue to be addressed in today's system-on-a-
chip (SoC) designs. One way to lower power consumption is to reduce the supply voltage …

In the last decade, improvements on technology scaling have enabled the design of a novel
generation of wearable biosensing monitors. These smart Wireless Body Sensor Nodes …

Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route
design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for …

Many enterprise and mobile systems must operate within strict power constraints. These
systems dynamically trade off performance and power to maximize performance while …