Impact of process variability on write error rate and read disturbance in STT-MRAM devices

J Song, H Dixit, B Behin-Aein, CH Kim… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Spin-transfer torque magnetic random-access memory (STT-MRAM) is the most promising
next-generation memory technology that combines the advantages of mainstream memory …

Exploiting STT-MRAMs for cryogenic non-volatile cache applications

E Garzón, R De Rose, F Crupi… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
This paper evaluates the potential of spin-transfer torque magnetic random-access
memories (STT-MRAMs) operating at cryogenic temperatures. Our study was carried out at …

Embedded memories for cryogenic applications

E Garzón, A Teman, M Lanuzza - Electronics, 2021 - mdpi.com
The ever-growing interest in cryogenic applications has prompted the investigation for
energy-efficient and high-density memory technologies that are able to operate efficiently at …

A variation-aware timing modeling approach for write operation in hybrid CMOS/STT-MTJ circuits

R De Rose, M Lanuzza, F Crupi… - … on Circuits and …, 2017 - ieeexplore.ieee.org
In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS
transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is …

Simulation analysis of DMTJ-based STT-MRAM operating at cryogenic temperatures

E Garzón, R De Rose, F Crupi… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
This article investigates spin-transfer torque magnetic random access memories (STT-
MRAMs) based on double-barrier magnetic tunnel junction (DMTJ) with two reference layers …

Ultralow voltage finFET-versus TFET-based STT-MRAM cells for IoT applications

E Garzón, M Lanuzza, R Taco, S Strangio - Electronics, 2021 - mdpi.com
Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic
tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile …

Compact modeling of perpendicular STT-MTJs with double reference layers

R De Rose, M d'Aquino, G Finocchio… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
This paper shows the steps to set up a simulation framework for perpendicular spin-transfer
torque (STT)-magnetic tunnel junctions (MTJs) with double-barrier and two antiparallel …

Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework

E Garzon, R De Rose, F Crupi, L Trojman… - Microelectronic …, 2019 - Elsevier
This paper deals with the technology scalability of spin-transfer torque magnetic RAMs (STT-
MRAMs) based on nanoscaled perpendicular magnetic tunnel junctions (MTJs) and FinFET …

Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework

E Garzon, R De Rose, F Crupi, L Trojman, G Finocchio… - Integration, 2020 - Elsevier
This paper explores non-volatile cache memories implemented by spin-transfer torque
magnetic random access memories (STT-MRAMs) based on state-of-the-art perpendicular …

Modular compact modeling of MTJ devices

MM Torunbalci, P Upadhyaya… - … on Electron Devices, 2018 - ieeexplore.ieee.org
This paper describes a robust, modular, and physics-based circuit framework to model the
conventional and emerging magnetic tunnel junction (MTJ) devices. Magnetization …