Single event upset (SEU) has become one of the major threats to dependable application
development targeted at safety systems in field programmable gate arrays (FPGAs). This …

Radiation particles can impact registers or memories creating soft errors. These errors can
modify more than one bit causing a multiple cell upset (MCU) which consists of errors in …

The reliability concern associated with radiation-induced soft errors in embedded memories
increases as semiconductor technology scales deep into the sub-40-nm regime. As the …

As technology scaling increases embedded static random access memory bit-cell density,
the number of soft errors due to radiation-induced multiple-bit upsets (MBUs) also increases …

Due to performance and reliability, network on chip (NoC) is considered to be the future
generation interconnect technique for multiple cores in a chip. This paper proposes a system …

SRAM-based field-programmable gate array (FPGA) vendors typically integrate error
correction codes (ECCs) into the configuration memory to assist designers in implementing …

Nanometric CMOS is likely to experience the occurrence of a single event causing a multiple-
node upset. This paper presents a novel memory cell design as variant of the DICE cell (that …

Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …

Tag array in on-chip caches is one of the most vulnerable components to radiation-induced
soft errors. Protecting the tag array in some processors is limited to error detection using the …

In a Nano-scale technology, reliability is one of the main issues for on-chip communication
systems. To make communication system more reliable, Joint Crosstalk Aware Multiple Error …