Comprehensive design space exploration of silicon photonic interconnects
The paper presents a comprehensive physical layer design and modeling platform for
silicon photonic interconnects. The platform is based on explicit closed-form expressions for …
silicon photonic interconnects. The platform is based on explicit closed-form expressions for …
Hybrid photonic-plasmonic nonblocking broadband 5× 5 router for optical networks
Photonic data routing in optical networks is expected to overcome the limitations of
electronic routers with respect to data rate, latency, and energy consumption. However …
electronic routers with respect to data rate, latency, and energy consumption. However …
Photonic crystal based routers for photonic integrated on chip networks: a brief analysis
D Shanmuga Sundar, R Sathyadevaki… - Optical and Quantum …, 2018 - Springer
Photonic integrated circuits are the devices in which multiple devices are integrated in a
single substrate to obtain the functionality of entire components as a single chip. In this …
single substrate to obtain the functionality of entire components as a single chip. In this …
Photonic crystal dynamic hitless routers for integrated photonic NoCs
Contemporary, emerging and exigent breakthroughs in chip multiprocessors (CMPs) lead to
atrocious performance and deficit communication between the processor cores in the …
atrocious performance and deficit communication between the processor cores in the …
Islands of heaters: A novel thermal management framework for photonic NoCs
Silicon photonics has become a promising candidate for future networks-on-chip (NoCs) as
it can enable high bandwidth density and lower latency with traversal of data at the speed of …
it can enable high bandwidth density and lower latency with traversal of data at the speed of …
8 x 8 wavelength router of optical network on chip
G Fan, R Orobtchouk, B Han, Y Li, H Li - Optics express, 2017 - opg.optica.org
An integrated 8 x 8 wavelength router based on the micro-ring resonators using 2 x 2 multi-
interference (MMI) crossing is demonstrated on silicon-on-insulator (SOI) technology, which …
interference (MMI) crossing is demonstrated on silicon-on-insulator (SOI) technology, which …
A fault check graph approach for photonic router in network on chip
A Zhu, D Chen, C Xu, C Hu… - 2018 IEEE 27th Asian Test …, 2018 - ieeexplore.ieee.org
Photonic Network-on-Chip (PNoC) has been a new trend for next generation multi-
processor system. However, components, such as Micro-Ring Resonators (MRRs), in PNoC …
processor system. However, components, such as Micro-Ring Resonators (MRRs), in PNoC …
Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems
This paper presents a novel scheduling approach that efficiently schedules the
computational and the communicational resources of a Software-Defined Photonic Network …
computational and the communicational resources of a Software-Defined Photonic Network …
Evaluating the influence of user searches on neighbors
Big Data rise made traditional data management techniques inadequate in many real life
scenarios. In particular, the availability of huge amounts of data pertaining to user …
scenarios. In particular, the availability of huge amounts of data pertaining to user …
PID controlled thermal management in photonic network-on-chip
The communication bandwidth and power consumption of network-on-chip (NoC) are going
to meet their limits soon because of traditional metallic interconnects. Photonic NoC (PNoC) …
to meet their limits soon because of traditional metallic interconnects. Photonic NoC (PNoC) …