This paper presents an FPGA emulation-based fast network on chip (NoC) prototyping
framework, called dynamic reconfigurable NoC (DRNoC) emulation platform. The main …

Due to the increasing number of cores in Systems on Chip (SoCs), bus architectures have
suffered with limitations regarding performance. As applications demand higher bandwidth …

The network on chip (NoC) design process requires an adequate characterization of the
application running on it to optimize communication resources utilization and dimensioning …

The fifth-generation (5G) mobile network has significantly enhanced people's lives with
faster internet speed and more reliable connections. However, there is still insufficient …

The efficiency of networks-on-chip (NoC) is affected by related routing algorithms. This
paper aims to develop a reliable routing mechanism in 2D mesh-based NoCs based on …

Due to the multi-core processors, the importance of parallel workloads has increased
considerably. However, many-core chips demand new interconnection strategies, since …

3D Network on Chip (NoC) has emerged as a new platform to meet the performance
requirements and scaling challenges of System on Chip. More investigations require …

Abstract Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs
among latency, throughput, speed, and silicon area, and the correctness and performance of …

The topology of interconnection networks is the cardinal factor influencing the performance
of computer architecture. The most popularly used network topologies are Mesh and its …

MPSoC is becoming a much more prevalent design style, to achieve tight time-to-market
design goals, to maximize design reuse, to simplify the verification process and to provide …