As minimum feature size and pitch spacing further scale down, triple patterning lithography
is a likely 193 nm extension along the paradigm of double patterning lithography for 14-nm …

As the scale of integrated circuits keeps increasing, it is witnessed that there is a surge in the
research of electronic design automation (EDA) to make the technology node scaling …

As the feature size of semiconductor process further scales to sub-16 nm technology node,
triple patterning lithography (TPL) has been regarded as one of the most promising …

As minimum feature size and pitch spacing further decrease in advanced technology nodes,
many new design constraints and challenges are introduced, such as regularity, middle of …

In advanced technology nodes, layout decomposition (LD) and mask optimization (MO) are
two key stages in integrated circuit design. Due to the inconsistency of the objectives of …

As the transistor feature size keeps shrinking, manufacturability has become an urgent issue
in semiconductor industry. In order to improve the manufacturability, various resolution …

Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor
industry has been pushing the 193 nm immersion lithopgrahy using multiple patterning to …

For next-generation technology nodes, multiple patterning lithography (MPL) has emerged
as a key solution, eg, triple patterning lithography (TPL) for 14/11nm, and quadruple …

In this paper, we consider the triple patterning lithography layout decomposition problem. To
address the problem, a discrete relaxation theory is built. For designing a discrete relaxation …

Multiple patterning lithography has been recognized as one of the most promising solutions,
in addition to extreme ultraviolet lithography, directed self-assembly, nanoimprint …