This book presents an in-depth treatment of various power reduction and speed
enhancement techniques based on multiple supply and threshold voltages. A detailed …

Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is
presented. It was found that the main speed bottleneck of existing SAFF's is the cross …

Provides the only up-to-date source on the most recent advances in this often complex and
fascinating topic. The only book to be entirely devoted to clocking Clocking has become one …

A “Roadmap” is an extended look at the future of a chosen field of inquiry composed from
the collective knowledge of researchers in that field. The composition of a roadmap can …

Power consumption has become a major constraint in the design of processors today. To
optimize a processor for energy-efficiency requires an examination of energy-performance …

This is an introduction to the Classic Paper on MOSFET scaling by R. Dennard et al.,“Design
of Ion-Implanted MOSFET's with Very Small Physical Dimensions,” published in the IEEE …

2 counters and 4: 2 compressors have been widely used for multiplier implementations. In
this paper, a fast 5: 3 compressor is derived for high-speed multiplier implementations. The …

A fully integrated, phase-locked loop (PLL) clock generator/phase aligner for the POWER3
microprocessor has been designed using a 2.5-V, 0.40-/spl mu/m digital CMOS6S process …

There is arguably no field in greater need of a comprehensive handbook than computer
engineering. The unparalleled rate of technological advancement, the explosion of …

Future enhancement of system performance will decreasingly rely on reduction in transistor
dimensions. Rather, performance gains will increasingly come from improved hardware and …