Impact of voltage scaling on soft errors susceptibility of multicore server cpus

D Agiakatsikas, G Papadimitriou, V Karakostas… - Proceedings of the 56th …, 2023 - dl.acm.org
Microprocessor power consumption and dependability are both crucial challenges that
designers have to cope with due to shrinking feature sizes and increasing transistor counts …

Silent data errors: Sources, detection, and modeling

A Singh, S Chakravarty, G Papadimitriou… - 2023 IEEE 41st VLSI …, 2023 - ieeexplore.ieee.org
Chip manufacturers and hyperscalers are becoming increasingly aware of the problem
posed by Silent Data Errors (SDE) and are taking steps to address it. Major computing …

Silent data corruptions: The stealthy saboteurs of digital integrity

G Papadimitriou, D Gizopoulos… - 2023 IEEE 29th …, 2023 - ieeexplore.ieee.org
Silent Data Corruptions (SDCs) pose a significant threat to the integrity of digital systems.
These stealthy saboteurs silently corrupt data, remaining undetected by traditional error …

Boosting microprocessor efficiency: Circuit-and workload-aware assessment of timing errors

I Tsiokanos, G Papadimitriou… - 2021 IEEE …, 2021 - ieeexplore.ieee.org
Aggressive technology scaling and increased static and dynamic variability caused by
process, temperature, voltage, and aging effects make nanometer circuits prone to timing …

Estimating the failures and silent errors rates of cpus across isas and microarchitectures

D Gizopoulos, G Papadimitriou… - … IEEE International Test …, 2023 - ieeexplore.ieee.org
Silent data corruptions (SDCs) pose a significant challenge to the reliable operation of
modern microprocessors. As the need for enhanced performance and reliability continues to …

Suit: Secure undervolting with instruction traps

J Juffinger, S Kalinin, D Gruss, F Mueller - Proceedings of the 29th ACM …, 2024 - dl.acm.org
Modern CPUs dynamically scale voltage and frequency for efficiency. However, too low
voltages can result in security-critical errors. Hence, vendors use a generous safety margin …

Energy efficiency of out-of-order CPUs: Comparative study and microarchitectural hotspot characterization of RISC-V designs

O Chatzopoulos, G Papadimitriou… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
Building on the power of open-source RISC-V CPU designs at the register-transfer level
(RTL) we evaluate the energy efficiency of the state-of-the-art open-source out-of-order …

A high-level approach for energy efficiency improvement of fpgas by voltage trimming

M Safarpour, L Xun, GV Merrett… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Chip manufacturers define voltage margins on top of the “best-case” operational voltage of
their chips to ensure reliable functioning in the worst-case settings. The margins guarantee …

Radical-pilot and parsl: Executing heterogeneous workflows on HPC platforms

A Alsaadi, L Ward, A Merzky, K Chard… - 2022 IEEE/ACM …, 2022 - ieeexplore.ieee.org
Workflows applications are becoming increasingly important to support scientific discovery.
That is leading to a proliferation of workflow management systems and, thus, to a …

Automatic Software Tailoring for Optimal Performance

JM Aragón-Jurado, JC de la Torre… - IEEE Transactions …, 2023 - ieeexplore.ieee.org
Efficient green software solutions require being aware of the characteristics of both the
software and the hardware where it is executed. Separately optimizing them leads to …