Integrated packet bit error rate tester for 10G SERDES
HA Baumer, P Wang - US Patent 7,373,561, 2008 - Google Patents
7,035,228 B2 2001/OO 12288 A1* 2001 OO15664 A1 2001/OO17595 A1 2001, 0021953 A1
2002.0054569 A1* 2003/OOO9307 A1* 2003/0048781 A1* 2003/O12O791 A1 …
2002.0054569 A1* 2003/OOO9307 A1* 2003/0048781 A1* 2003/O12O791 A1 …
Multi-rate, multi-port, gigabit SERDES transceiver
HA Baumer - US Patent 7,355,987, 2008 - Google Patents
A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes
the flexibility to connect any one of the parallel ports to another parallel port or to a serial …
the flexibility to connect any one of the parallel ports to another parallel port or to a serial …
Multipurpose and programmable pad ring for an integrated circuit
HT Tran, HA Baumer - US Patent 7,664,888, 2010 - Google Patents
A multi-port SERDES transceiver includes multiple parallel and serial ports, and the
flexibility to connect any one of the parallel or serial ports to another parallel or serial port …
flexibility to connect any one of the parallel or serial ports to another parallel or serial port …
Multi-rate MAC to PHY interface
GS Huff, HA Baumer - US Patent 8,699,514, 2014 - Google Patents
A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer
(PHY) interface is provided. The method to provide a multi-rate Media Access Control layer …
(PHY) interface is provided. The method to provide a multi-rate Media Access Control layer …
Programmable management IO pads for an integrated circuit
HT Tran, HA Baumer - US Patent 7,533,311, 2009 - Google Patents
A multi-port SERDES transceiver includes multiple parallel and serial ports, and the
flexibility to connect any one of the parallel or serial ports to another parallel or serial port …
flexibility to connect any one of the parallel or serial ports to another parallel or serial port …
Circuit for improving noise immunity by DV/DT boosting
M Grasso, M Subaramanian - US Patent 6,611,154, 2003 - Google Patents
The circuit of the present invention advantageously over comes the above-noted
deficiencies of the prior art by Sensing the amount of current that must be Supplied to the …
deficiencies of the prior art by Sensing the amount of current that must be Supplied to the …
Multi-rate, multi-port, gigabit serdes transceiver
HA Baumer - US Patent 8,023,436, 2011 - Google Patents
A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and
includes the flexibility to connect any one of the parallel ports to another parallel port or to a …
includes the flexibility to connect any one of the parallel ports to another parallel port or to a …
Multi-port, gigabit serdes transceiver capable of automatic fail switchover
H Tran - US Patent 8,385,188, 2013 - Google Patents
(51) Int. Cl. A multi-port Serdes transceiver includes multiple parallel G06F II/00(2006.01)
ports and serial ports, and includes the flexibility to connect (52) US Cl …
ports and serial ports, and includes the flexibility to connect (52) US Cl …
Cross link multiplexer bus
A Amirichimeh, H Baumer, D Oda - US Patent 7,450,529, 2008 - Google Patents
Preferably, the plurality of cross link multiplexers includes a delay buffer to delay
conveyance of a first bit so that it remains substantially synchronized with a second bit …
conveyance of a first bit so that it remains substantially synchronized with a second bit …
Cross link multiplexer bus configured to reduce cross-talk
A Amirichimeh, H Baumer, D Oda - US Patent 7,450,530, 2008 - Google Patents
Krs: sented as a first data bit, a second data bit, and a control bit. A first interconnect is
configured to convey the first data bit. A second interconnect is configured to convey the …
configured to convey the first data bit. A second interconnect is configured to convey the …