Board-level drop impact testing is a useful way to characterize the drop durability of the
different soldered assemblies onto the printed circuit board (PCB). The characterization …

Modeling approaches for first-level solder interconnects in shock and drop of electronics
assemblies have been developed without any assumptions of geometric symmetry or …

In this review, some major aspects of the current underfill technologies for flip-chip (FC) and
fine-pitch-ball-grid-array (FPBGA), including chip-size packaging (CSP), are addressed, with …

Product level assessment of drop and shock reliability relies heavily on experimental test
methods. Prediction of drop and shock survivability is largely beyond the state-of-art …

Many studies on eutectic solder by Amagai in 1999, Sharma and Dasgupta in 2003 and
Zhai, Sidharth and Blish in 2003 have shown that the dwell time beyond certain limit has a …

Portable electronics is subjected to extreme accelerations in shock and drop impact. Product
development cycle times and the cost constraints often restrict the number of design …

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure.
The current version of BIST approach is focused on reactive failure detection and provides …

Electronics may be subjected to shock, vibration, and drop-impact during shipping, handling
and during normal usage. Measurement of transient dynamic deformation of the electronics …

Relative damage-index based on the leadfree interconnect transient strain history from
digital image correlation, explicit finite-elements, cohesive-zone elements, and component's …

A technique has been developed for monitoring the structural damage accrued in ball grid
array interconnects during operation in vibration environments. The technique uses …