Minimizing the supply sensitivity of a CMOS ring oscillator through jointly biasing the supply and control voltages
A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through
joint biasing of the supply and the control voltage. The technique can supplement a number …
joint biasing of the supply and the control voltage. The technique can supplement a number …
A 2.5-GHz built-in jitter measurement system in a serial-link transceiver
SY Jiang, KH Cheng, PY Jian - IEEE transactions on very large …, 2009 - ieeexplore.ieee.org
A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on
a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce …
a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce …
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction
L Xie, Z Dong, J Sun, S Gao, S Li, N Jing… - … on Circuits and …, 2024 - ieeexplore.ieee.org
This paper presents a period jitter measurement circuit that employs a stochastic phase
interpolation scheme. Triggered by an input clock, a delay line is applied to sample the …
interpolation scheme. Triggered by an input clock, a delay line is applied to sample the …
An iddq bist approach to characterize phase-locked loop parameters
S Maltabas, OK Ekekon, K Kulovic… - 2013 IEEE 31st VLSI …, 2013 - ieeexplore.ieee.org
In this work, a new IDDQ built-in self-test (BIST) solution is proposed to provide accurate on-
chip current measurements for phase-locked loops (PLLs) found in deep-submicron system …
chip current measurements for phase-locked loops (PLLs) found in deep-submicron system …
A pilot study of applying hierarchical curriculum structure graph for remedial learning
YL Wu - Seventh IEEE International Conference on Advanced …, 2007 - ieeexplore.ieee.org
" Conceptual graphs" is a conventionally adopted assisted teaching method. Conceptual
graphs display the achievements of students. The framework of learning activity is based on …
graphs display the achievements of students. The framework of learning activity is based on …
Adaptive low-jitter LC-based clock distribution
L Lee, CKK Yang - 2007 IEEE International Solid-State Circuits …, 2007 - ieeexplore.ieee.org
A low-jitter LC-based clock distribution in 0.13 μm CMOS uses a frequency-tuning technique
based on a voltage-swing digitizer. Optimum jitter performance is achieved by adaptively …
based on a voltage-swing digitizer. Optimum jitter performance is achieved by adaptively …
Time-to-digital conversion
A Majumdar, SC Nimmagadda, B Sadasivam… - US Patent …, 2014 - Google Patents
US8884804B1 - Time-to-digital conversion - Google Patents US8884804B1 - Time-to-digital
conversion - Google Patents Time-to-digital conversion Download PDF Info Publication …
conversion - Google Patents Time-to-digital conversion Download PDF Info Publication …
Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors
S Kundu - 2016 - search.proquest.com
Digital intensive circuit design techniques of different mixed-signal systems such as data
converters, clock generators, voltage regulators etc. are gaining attention for the …
converters, clock generators, voltage regulators etc. are gaining attention for the …
[图书][B] Configurable frequency synthesizer for large scale physics experiments
N Parkalian - 2019 - juser.fz-juelich.de
This thesis describes the design and implementation of frequency synthesizers for the”
Jiangmen Underground Neutrino Observatory (JUNO)” project as a physical experiment …
Jiangmen Underground Neutrino Observatory (JUNO)” project as a physical experiment …
A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor
In this brief, a frequency-to-current conversion-based fractional frequency synthesizer is
implemented in 32-nm technology utilizing a high-density deep trench capacitor. The …
implemented in 32-nm technology utilizing a high-density deep trench capacitor. The …