Design and development of a novel MOSFET structure for reduction of reverse bias pn junction leakage current

D Mukherjee, BVR Reddy - International Journal of …, 2020 - inderscienceonline.com
Present world is acquainted with the plethora of battery operated portable electronic goods
in leaps and bounds. For long life of battery, it is very imperative to minimise the leakage …

Leakage power reduction techniques of 55 nm SRAM cells

LJ Zhang, C Wu, YQ Ma, JB Zheng… - IETE technical Review, 2011 - Taylor & Francis
As the technology scales down to 90 nm and below, static random access memory (SRAM)
standby leak-age power is becoming one of the most critical concerns for low power …

Design and Investigation of Split Gate Dielectric Modulated JLFET for Detection of Biological Molecule Using TCAD Simulation

R Mandal, D Mukherjee - Silicon, 2023 - Springer
Here, a split gate insulator-controlled Junction less FET also known as SG-DM-JLFET is
investigated and proposed to recognize biomolecules such as uricase, biotin, or …

Read stability and power analysis of a proposed novel 8 transistor static random access memory cell in 45 nm technology

P Upadhyay, R Kar, D Mandal, SP Ghoshal - 2014 - sid.ir
This paper presents analysis of the STATIC NOISE MARGIN (SNM), power dissipation,
ACCESS TIME and dynamic noise margin of a novel low power proposed 8T Static Random …

Analysis Of PN Junction Length of Drain and Source in MOSFET Transistor Through TCAD Simulation

D Mukherjee, PK Sanda… - Journal of Electrical …, 2024 - search.proquest.com
This paper delves into the convergence of mathematical and computer science principles
within the realm of electronics engineering, particularly focusing on device-level transistor …

Algorithm design, software simulation and mathematical modelling of subthreshold leakage current in CMOS circuits

D Mukherjee, BVR Reddy - International Journal of …, 2019 - inderscienceonline.com
In this paper, concepts of mathematics and computer science were applied to electronics
engineering field, specifically very large scale integration (VLSI) design and semiconductor …

Effect of Multi Threshold Techniques on Comparative Study of 11T and 6T Cell During Leakage Power Robustness

YS Randhawa, S Sharma - Quantum Matter, 2013 - ingentaconnect.com
An 11T transistor cell at 45 nanometer is proposed to overcome the leakage components
during the operations, compared with conventional 6T SRAM cell. The leakage components …

[PDF][PDF] Comparison of three techniques for leakage current minimization in CMOS VLSI Circuit in 90 nm technology

D Mukherjee, BVR Reddy, G Perveen… - Int J Recent Trends …, 2010 - researchgate.net
Today VLSI circuit fabrication technology has reached in nanometer dimension. When
CMOS technology superseded BJT technology, very low leakage current was one of the …

Design of cost effective transistor by software simulation for profitable production

D Mukherjee, BVR Reddy - International Journal of …, 2020 - inderscienceonline.com
Reduction of process cost is the key factor for profitability in any industry. Semiconductor
industry is also not an exception of this rule. In this paper, a novel transistor structure has …

[PDF][PDF] Technical Review

T Engineers - IETE Technical Review, 2009 - researchgate.net
Wireless communication systems have evolved over the ages. However, there are some
undesirable effects of a wireless communication channel on the signals transmitted through …