Exploring serial vertical interconnects for 3D ICs
S Pasricha - Proceedings of the 46th Annual Design Automation …, 2009 - dl.acm.org
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-
chip communication bottleneck and improve performance over traditional two-dimensional …
chip communication bottleneck and improve performance over traditional two-dimensional …
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
S Bahirat, S Pasricha - ACM Transactions on Embedded Computing …, 2014 - dl.acm.org
With increasing application complexity and improvements in process technology, Chip
MultiProcessors (CMPs) with tens to hundreds of cores on a chip are becoming a reality …
MultiProcessors (CMPs) with tens to hundreds of cores on a chip are becoming a reality …
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
S Bahirat, S Pasricha - Proceedings of the 7th IEEE/ACM international …, 2009 - dl.acm.org
Increasing application complexity and improvements in process technology have today
enabled chip multiprocessors (CMPs) with tens to hundreds of cores on a chip. Networks on …
enabled chip multiprocessors (CMPs) with tens to hundreds of cores on a chip. Networks on …
Two high-performance and low-power serial communication interfaces for on-chip interconnects
M Saneei, A Afzali-Kusha… - Canadian Journal of …, 2009 - ieeexplore.ieee.org
This paper presents two novel methods for on-chip serial communication in which the clocks
of the transmitter and the receiver are generated with two separate ring oscillators. These …
of the transmitter and the receiver are generated with two separate ring oscillators. These …
Design of a serialized link for on-chip global communication
A Kedia - 2006 - open.library.ubc.ca
On-chip global communication is required for data and control transfers across various
modules on the chip and determines the performance of the integrated circuit in current …
modules on the chip and determines the performance of the integrated circuit in current …
A mesochronous technique for communication in network on chips
M Saneei, A Afzali-Kusha… - … international conference on …, 2006 - ieeexplore.ieee.org
In this paper, we propose a mesochronous scheme for communication over serial buses in
network on chips (NoC). The technique, which removes metastability errors in …
network on chips (NoC). The technique, which removes metastability errors in …
A portable all-digital pulsewidth control loop for SOC applications
A cell-based all-digital PWCL is presented in this paper. To improve design effort as well as
facilitate system-level integration, the new design can be developed in hardware description …
facilitate system-level integration, the new design can be developed in hardware description …
Through Silicon Via Virtualization for Fault-Tolerant Multi-Protocol Interconnect in 3D-ICs
FR Miller - 2018 - mediatum.ub.tum.de
3D-ICs with through silicon vias (TSVs) allow multiplication of circuit capacities with constant
area footprint. This dissertation covers the optimization of on-chip communication networks …
area footprint. This dissertation covers the optimization of on-chip communication networks …
Design and synthesis of hybrid nanophotonic-electric network-on-chip architectures
S Bahirat - 2014 - search.proquest.com
With increasing application complexity and improvements in CMOS process technology,
chip multiprocessors (CMPs) with tens to hundreds of cores on a chip are today becoming a …
chip multiprocessors (CMPs) with tens to hundreds of cores on a chip are today becoming a …
On-Chip Optical Ring Bus Communication Architecture for Heterogeneous MPSoC
S Pasricha, ND Dutt - Integrated Optical Interconnect Architectures for …, 2013 - Springer
With increasing application complexity and improvements in process technology, multi-
processor systems-on-chip (MPSoC) with tens to hundreds of cores on a chip are being …
processor systems-on-chip (MPSoC) with tens to hundreds of cores on a chip are being …