Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in
chip multiprocessors and system-on-chip designs. Existing interconnection networks use …

Driven by continuing scaling of Moore's law, chip multi-processors and systems-on-a-chip
are expected to grow the core count from dozens today to hundreds in the near future …

Interconnection networks enable fast data communication between components of a digital
system. Today, interconnection networks are used in a variety of applications such as switch …

As modern CMPs scale to ever increasing core counts, Networks-on-Chip (NoCs) are
emerging as an interconnection fabric, enabling communication between components …

In this paper, we propose a new congestion management strategy for lossless multistage
interconnection networks that scales as network size and/or link bandwidth increase. Instead …

With the rapid development of semiconductor industry, the number of cores integrated on
chip increases quickly, which brings tough challenges such as bandwidth, scalability and …

In chip design today and for a foreseeable future, the last-level cache and on-chip
interconnect is not only performance critical but also a substantial power consumer. This …

Network congestion can limit performance of NoC due to increased transmission latency
and power consumption. Congestion-aware adaptive routing can greatly improve the …

Congestion occurs frequently in Networks-on-Chip when the packets demands exceed the
capacity of network resources. Congestion-aware routing algorithms can greatly improve the …

BACKGROUND Chip-level multiprocessors combine two or more indepen dent processing
nodes on a single integrated circuit. These processing architectures have emerged as the …