Integrated circuit chip using top post-passivation technology and bottom structure technology
M Lin, J Lee, H Lo, P Yang, T Liu - US Patent 8,456,856, 2013 - freepatentsonline.com
Integrated circuit chips and chip packages are disclosed that include an over-passivation
scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the …
scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the …
Djinn and tonic: Dnn as a service and its implications for future warehouse scale computers
As applications such as Apple Siri, Google Now, Microsoft Cortana, and Amazon Echo
continue to gain traction, web-service companies are adopting large deep neural networks …
continue to gain traction, web-service companies are adopting large deep neural networks …
Optical I/O technology for tera-scale computing
IA Young, E Mohammed, JTS Liao… - IEEE Journal of solid …, 2009 - ieeexplore.ieee.org
This paper describes both a near term and a long term optical interconnect solution, the first
based on a packaging architecture and the second based on a monolithic photonic CMOS …
based on a packaging architecture and the second based on a monolithic photonic CMOS …
The new era of scaling in an SoC world
M Bohr - 2009 IEEE International Solid-State Circuits …, 2009 - ieeexplore.ieee.org
The time has passed when traditional MOSFET scaling techniques were adequate to meet
the needs of microprocessor products, but that has not meant the end of Moore's Law nor the …
the needs of microprocessor products, but that has not meant the end of Moore's Law nor the …
Top layers of metal for high performance IC's
MS Lin - US Patent 8,531,038, 2013 - Google Patents
(57) ABSTRACT A method of closely interconnecting integrated circuits con tained within a
semiconductor wafer to electrical circuits Surrounding the semiconductor wafer. Electrical …
semiconductor wafer to electrical circuits Surrounding the semiconductor wafer. Electrical …
A family of 45nm IA processors
R Kumar, G Hinton - … Solid-State Circuits Conference-Digest of …, 2009 - ieeexplore.ieee.org
Nehalem is a family of next-generation IA processors for mobile, desktop and server
segments implemented in 45nm high-kappa metal-gate CMOS. The family features a new …
segments implemented in 45nm high-kappa metal-gate CMOS. The family features a new …
System-in packages
MS Lin, JY Lee - US Patent 8,503,186, 2013 - Google Patents
H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …
state devices; Multistep manufacturing processes thereof the devices being of types …
A 45 nm 8-core enterprise Xeon processor
S Rusu, S Tam, H Muljono, J Stinson… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor
with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock …
with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock …
A 3x9 Gb/s shared, all-digital CDR for high-speed, high-density I/O
M Loh, A Emami-Neyestanak - IEEE Journal of Solid-State …, 2012 - ieeexplore.ieee.org
This paper presents a novel all-digital CDR scheme in 90 nm CMOS. Two independently
adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase …
adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase …
Image and light sensor chip packages
MS Lin, JY Lee - US Patent 8,193,555, 2012 - Google Patents
An image or light sensor chip package includes an image or light sensor chip having a non-
photosensitive area and a pho tosensitive area Surrounded by the non-photosensitive area …
photosensitive area and a pho tosensitive area Surrounded by the non-photosensitive area …