Design and implementation of a new real-time frequency sensor used as hardware countermeasure
R Jiménez-Naharro, JA Gómez-Galán… - Sensors, 2013 - mdpi.com
A new digital countermeasure against attacks related to the clock frequency is–presented.
This countermeasure, known as frequency sensor, consists of a local oscillator, a transition …
This countermeasure, known as frequency sensor, consists of a local oscillator, a transition …
Impact of gate-leakage currents on CMOS circuit performance
A Marras, I De Munari, D Vescovi… - Microelectronics …, 2005 - Elsevier
Ultra-thin gate dielectrics are exploited in fabrication of MOSFETs featuring channel lengths
in the decananometer range: according to the ITRS oxide thickness in the order of 1nm will …
in the decananometer range: according to the ITRS oxide thickness in the order of 1nm will …
Selective clock-gating for low power/low noise synchronous counters
P Parra, A Acosta, M Valencia - … Workshop on Power and Timing Modeling …, 2002 - Springer
The objective of this paper is to explore the applicability of clock gating techniques to binary
counters in order to reduce the power consumption as well as the switching noise …
counters in order to reduce the power consumption as well as the switching noise …
Selective Clock-Gating for Low-Power Synchronous Counters
With current technologies and applications, dynamic power reduction is of great
technological interest. The objective of this paper is to explore the applicability of clock …
technological interest. The objective of this paper is to explore the applicability of clock …
VLSI Implementation of digital frequency sensors as hardware countermeasure
Non-invasive attacks are considered among the more serious threats for the hardware
security due to there not exist evidences of them. Among these attacks, the clock glitch attack …
security due to there not exist evidences of them. Among these attacks, the clock glitch attack …
Logic-level fast current simulation for digital cmos circuits
P Ruiz de Clavijo, J Juan-Chico… - … Workshop on Power …, 2005 - Springer
Nowadays, verification of digital integrated circuit has been focused more and more from the
timing and area field to current and power estimations. The main problem with this kind of …
timing and area field to current and power estimations. The main problem with this kind of …
Low-standby-current and high-speed SAFF with improved conditional-precharge modules
A new low-power and high-speed sense-amplifier-based flip-flop with improved conditional-
precharge modules (LSCP-SAFF) is proposed. By employing a modified differential latch …
precharge modules (LSCP-SAFF) is proposed. By employing a modified differential latch …
A new hybrid CBL-CMOS cell for optimum noise/power application
The design of a new configurable hybrid current-mode/static CBL-CMOS cell is presented.
This cell can be used in order to obtain the optimum partitioning between conventional and …
This cell can be used in order to obtain the optimum partitioning between conventional and …
Integrated Circuit and System Design
VPJ Vounckx, D Verkest - Springer
Welcome to the proceedings of PATMOS 2005, the 15th in a series of international
workshops. PATMOS 2005 was organized by IMEC with technical co-sponsorship from the …
workshops. PATMOS 2005 was organized by IMEC with technical co-sponsorship from the …
Optimization of master-slave flip-flops for high-performance applications
The design of high-performance master-slave flip-flops is of crucial importance in modern
VLSI. The optimization of existing structures is necessary when the requirements of the flip …
VLSI. The optimization of existing structures is necessary when the requirements of the flip …